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From: "Miao, Jun" <jun.miao@intel.com>
To: Borislav Petkov <bp@alien8.de>
Cc: "tglx@kernel.org" <tglx@kernel.org>,
	"mingo@redhat.com" <mingo@redhat.com>,
	"dave.hansen@linux.intel.com" <dave.hansen@linux.intel.com>,
	"m.szyprowski@samsung.com" <m.szyprowski@samsung.com>,
	"robin.murphy@arm.com" <robin.murphy@arm.com>,
	"Edgecombe, Rick P" <rick.p.edgecombe@intel.com>,
	"x86@kernel.org" <x86@kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"aakarsh.jain@oss.qualcomm.com" <aakarsh.jain@oss.qualcomm.com>,
	"michael.roth@amd.com" <michael.roth@amd.com>,
	"Du, Fan" <fan.du@intel.com>
Subject: RE: [PATCH v4] x86/pci-dma: add a SWIOTLB_ANY flag to lift the low mem limitation
Date: Thu, 23 Jul 2026 10:21:22 +0000	[thread overview]
Message-ID: <PH7PR11MB8455A4FDECB27FA0B052FDCD9AC02@PH7PR11MB8455.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20260712005547.GBalLmE0FTJYx7Cnwg@fat_crate.local>


>On Thu, Jun 25, 2026 at 09:26:16AM +0800, Jun Miao wrote:
>> When high-speed NICs or multi-GPU setups are passed through into
>> confidential VMs, the SWIOTLB bounce buffer becomes the critical path
>> between private and shared memory. Restricting it to low memory limits
>> throughput and fails to scale for larger workloads.
>>
>> AMD SEV-SNP and Intel TDX guests run in a TEE where the hypervisor is
>untrusted.
>> DMA-capable devices require bounce buffers to mediate between
>> encrypted private memory and unencrypted shared memory. Confining
>> these buffers to low memory (<4GB) unnecessarily caps their size and
>degrades performance.
>>
>> Power SVM already supports this; x86 does not. See commit 8ba2ed1be9
>> ("swiotlb: add a SWIOTLB_ANY flag to lift the low memory restriction").
>>
>> [ aakarsh: completely trim down/rewrite changelog ]
>>
>> Tested-by: Aakarsh Jain <aakarsh.jain@oss.qualcomm.com>
>> Suggested-by: Borislav Petkov <bp@alien8.de>
>> Acked-by: Marek Szyprowski <m.szyprowski@samsung.com>
>> Reviewed-by: Aakarsh Jain <aakarsh.jain@oss.qualcomm.com>
>> Signed-off-by: Jun Miao <jun.miao@intel.com>
>> ---
>
>Sashiko has a question:
>
>https://lore.kernel.org/r/20260625012616.2992535-1-jun.miao@intel.com
>
>
Sashiko  said “Does x86 lack DMA-mask filtering during pool search?”:

Conclusion:  yes, it does (at least in the current common SWIOTLB search path).
Therefore, after enabling SWIOTLB_ANY, dma-direct with 32-bit DMA-mask devices is indeed more
likely to hit the case where a high-address bounce buffer is allocated first and then rejected by dma_capable().

I plan to modify SWIOTLB directly: in the direct DMA path, I’ll filter candidate pool/slot addresses by dma_capable() 
during the search phase, so we avoid the case where a high address is allocated first and then fails without retrying 
a low-memory buffer. At the same time, I’ll keep the IOMMU/Xen paths unchanged.

Warm regards
Jun Miao
>--
>Regards/Gruss,
>    Boris.
>
>https://people.kernel.org/tglx/notes-about-netiquette

      reply	other threads:[~2026-07-23 10:21 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-06-25  1:26 Jun Miao
2026-06-25  3:14 ` Michael Kelley
2026-07-12  0:55 ` Borislav Petkov
2026-07-23 10:21   ` Miao, Jun [this message]

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