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Thu, 27 Mar 2025 10:54:50 +0000 From: Tarang Raval To: Sakari Ailus CC: "kieran.bingham@ideasonboard.com" , "Shravan.Chippa@microchip.com" , Mauro Carvalho Chehab , Hans Verkuil , Laurent Pinchart , Umang Jain , Zhi Mao , Julien Massot , Luis Garcia , Benjamin Mugnier , "linux-media@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH 4/6] media: i2c: imx334: Support 4 or 8 lane operation modes Thread-Topic: [PATCH 4/6] media: i2c: imx334: Support 4 or 8 lane operation modes Thread-Index: AQHbkYze21WXVq2lI0WizvQdhNA/mLOG3YiAgAAHtdU= Date: Thu, 27 Mar 2025 10:54:50 +0000 Message-ID: References: <20250310071751.151382-1-tarang.raval@siliconsignals.io> <20250310071751.151382-5-tarang.raval@siliconsignals.io> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=siliconsignals.io; x-ms-publictraffictype: Email x-ms-traffictypediagnostic: PN3P287MB1829:EE_|MAZP287MB0542:EE_ x-ms-office365-filtering-correlation-id: 13eeeafb-40d1-4750-debd-08dd6d1dcc2d x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0;ARA:13230040|1800799024|366016|7416014|376014|38070700018; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: siliconsignals.io X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PN3P287MB1829.INDP287.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-Network-Message-Id: 13eeeafb-40d1-4750-debd-08dd6d1dcc2d X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Mar 2025 10:54:50.2943 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 7ec5089e-a433-4bd1-a638-82ee62e21d37 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: HcdV71aIb/5FSji/rucJxNuqgLP2CqWJWk9tkerC7PNOc8Gn4oPI+u77tR/RunLAdGO8SAp1PPjKXju2d/SBsO0z7eE+G2D0yTY6E/WaUQ4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MAZP287MB0542 Hi Sakari,=0A= =0A= Thanks for the review.=0A= =0A= > On Mon, Mar 10, 2025 at 12:47:46PM +0530, Tarang Raval wrote:=0A= > > imx334 can support both 4 and 8 lane configurations.=0A= > > Extend the driver to configure the lane mode accordingly.=0A= > >=0A= > > Signed-off-by: Tarang Raval =0A= > > ---=0A= > > =A0drivers/media/i2c/imx334.c | 22 +++++++++++++++++++---=0A= > > =A01 file changed, 19 insertions(+), 3 deletions(-)=0A= > >=0A= > > diff --git a/drivers/media/i2c/imx334.c b/drivers/media/i2c/imx334.c=0A= > > index 24ccfd1d0986..23bfc64969cc 100644=0A= > > --- a/drivers/media/i2c/imx334.c=0A= > > +++ b/drivers/media/i2c/imx334.c=0A= > > @@ -47,6 +47,8 @@=0A= > > =A0#define IMX334_EXPOSURE_DEFAULT =A0 =A0 =A00x0648=0A= > >=0A= > > =A0#define IMX334_REG_LANEMODE =A0 =A0 =A0 =A0 =A0 =A0CCI_REG8(0x3a01)= =0A= > > +#define IMX334_CSI_4_LANE_MODE =A0 =A0 =A0 =A0 3=0A= > > +#define IMX334_CSI_8_LANE_MODE =A0 =A0 =A0 =A0 7=0A= > >=0A= > > =A0/* Window cropping Settings */=0A= > > =A0#define IMX334_REG_AREA3_ST_ADR_1 =A0 =A0 =A0CCI_REG16_LE(0x3074)=0A= > > @@ -107,7 +109,6 @@=0A= > > =A0/* CSI2 HW configuration */=0A= > > =A0#define IMX334_LINK_FREQ_891M =A0 =A0 =A0 =A0891000000=0A= > > =A0#define IMX334_LINK_FREQ_445M =A0 =A0 =A0 =A0445500000=0A= > > -#define IMX334_NUM_DATA_LANES =A0 =A0 =A0 =A04=0A= > >=0A= > > =A0#define IMX334_REG_MIN =A0 =A0 =A0 =A0 =A0 =A0 =A0 0x00=0A= > > =A0#define IMX334_REG_MAX =A0 =A0 =A0 =A0 =A0 =A0 =A0 0xfffff=0A= > > @@ -181,6 +182,7 @@ struct imx334_mode {=0A= > > =A0 * @exp_ctrl: Pointer to exposure control=0A= > > =A0 * @again_ctrl: Pointer to analog gain control=0A= > > =A0 * @vblank: Vertical blanking in lines=0A= > > + * @lane_mode: Mode for number of connected data lanes=0A= > > =A0 * @cur_mode: Pointer to current selected sensor mode=0A= > > =A0 * @mutex: Mutex for serializing sensor controls=0A= > > =A0 * @link_freq_bitmap: Menu bitmap for link_freq_ctrl=0A= > > @@ -204,6 +206,7 @@ struct imx334 {=0A= > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 struct v4l2_ctrl *again_ctrl;=0A= > > =A0 =A0 =A0 };=0A= > > =A0 =A0 =A0 u32 vblank;=0A= > > + =A0 =A0 u32 lane_mode;=0A= > > =A0 =A0 =A0 const struct imx334_mode *cur_mode;=0A= > > =A0 =A0 =A0 struct mutex mutex;=0A= > > =A0 =A0 =A0 unsigned long link_freq_bitmap;=0A= > > @@ -240,7 +243,6 @@ static const struct cci_reg_sequence common_mode_re= gs[] =3D {=0A= > > =A0 =A0 =A0 { IMX334_REG_HADD_VADD, 0x00},=0A= > > =A0 =A0 =A0 { IMX334_REG_VALID_EXPAND, 0x03},=0A= > > =A0 =A0 =A0 { IMX334_REG_TCYCLE, 0x00},=0A= > > - =A0 =A0 { IMX334_REG_LANEMODE, 0x03},=0A= >=A0=0A= > Not a fault of this patch but also the closing brace should have a space= =0A= > before it. Could you address it in the earlier patches?=0A= =0A= Okay, I will correct it.=0A= =0A= > > =A0 =A0 =A0 { IMX334_REG_TCLKPOST, 0x007f},=0A= > > =A0 =A0 =A0 { IMX334_REG_TCLKPREPARE, 0x0037},=0A= > > =A0 =A0 =A0 { IMX334_REG_TCLKTRAIL, 0x0037},=0A= > > @@ -876,6 +878,13 @@ static int imx334_start_streaming(struct imx334 *i= mx334)=0A= > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 return ret;=0A= > > =A0 =A0 =A0 }=0A= > >=0A= > > + =A0 =A0 ret =3D cci_write(imx334->cci, IMX334_REG_LANEMODE,=0A= > > + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 imx334->lane_mode, NULL);=0A= > > + =A0 =A0 if (ret) {=0A= > > + =A0 =A0 =A0 =A0 =A0 =A0 dev_err(imx334->dev, "failed to configure lan= es\n");=0A= > > + =A0 =A0 =A0 =A0 =A0 =A0 return ret;=0A= > > + =A0 =A0 }=0A= > > +=0A= > > =A0 =A0 =A0 ret =3D imx334_set_framefmt(imx334);=0A= > > =A0 =A0 =A0 if (ret) {=0A= > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 dev_err(imx334->dev, "%s failed to set fram= e format: %d\n",=0A= > > @@ -1022,7 +1031,14 @@ static int imx334_parse_hw_config(struct imx334 = *imx334)=0A= > > =A0 =A0 =A0 if (ret)=0A= > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 return ret;=0A= > >=0A= > > - =A0 =A0 if (bus_cfg.bus.mipi_csi2.num_data_lanes !=3D IMX334_NUM_DATA= _LANES) {=0A= > > + =A0 =A0 switch (bus_cfg.bus.mipi_csi2.num_data_lanes) {=0A= > > + =A0 =A0 case 4:=0A= > > + =A0 =A0 =A0 =A0 =A0 =A0 imx334->lane_mode =3D IMX334_CSI_4_LANE_MODE;= =0A= > > + =A0 =A0 =A0 =A0 =A0 =A0 break;=0A= > > + =A0 =A0 case 8:=0A= > > + =A0 =A0 =A0 =A0 =A0 =A0 imx334->lane_mode =3D IMX334_CSI_8_LANE_MODE;= =0A= >=A0=0A= > Doesn't this affect the PLL configuration? Presumably higher frame rates= =0A= > could be achieved at least.=0A= =0A= Sorry, my commit message is misleading. The intention of this patch is to= =0A= configure the lane mode dynamically from the streaming function instead =0A= of using a hardcoded value.=0A= =0A= You are correct that supporting an 8-lane mode requires changes to the PLL= =0A= configuration. This patch does not address that aspect yet.=0A= =0A= Best Regards,=0A= Tarang=0A= > > + =A0 =A0 =A0 =A0 =A0 =A0 break;=0A= > > + =A0 =A0 default:=0A= > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 dev_err(imx334->dev,=0A= > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 "number of CSI2 data lanes = %d is not supported\n",=0A= > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 bus_cfg.bus.mipi_csi2.num_d= ata_lanes);=0A= >=A0=0A= > --=0A= > Regards,=0A= >=A0=0A= > Sakari Ailus=