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SoC To: Bjorn Helgaas References: From: Chen Wang Cc: Chen Wang , kwilczynski@kernel.org, u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, alex@ghiti.fr, arnd@arndb.de, bwawrzyn@cisco.com, bhelgaas@google.com, conor+dt@kernel.org, 18255117159@163.com, inochiama@gmail.com, kishon@kernel.org, krzk+dt@kernel.org, lpieralisi@kernel.org, mani@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org, s-vadapalli@ti.com, tglx@linutronix.de, thomas.richard@bootlin.com, sycamoremoon376@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, rabenda.cn@gmail.com, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com, jeffbai@aosc.io In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: SGXP274CA0003.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b8::15) To PN4PR01MB11064.INDPRD01.PROD.OUTLOOK.COM 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MA0PR01MB9078 Hello, Bjorn, Is it ok for you to pick this patchset, so we can see this in next 6.18. You can pick [1/7]~[3/7], I can handle the left dts part. Thanks, Chen On 9/12/2025 10:35 AM, Chen Wang wrote: > From: Chen Wang > > Sophgo's SG2042 SoC uses Cadence PCIe core to implement RC mode. > > This is a completely rewritten PCIe driver for SG2042. It inherits > some previously submitted patch codes (not merged into the upstream > mainline), but the biggest difference is that the support for > compatibility with old 32-bit PCIe devices has been removed in this > new version. This is because after discussing with community users, > we felt that there was not much demand for support for old devices, > so we made a new design based on the simplified design and practical > needs. If someone really needs to play with old devices, we can provide > them with some necessary hack patches in the downstream repository. > > Since the new design is quite different from the old code, I will > release it as a new patch series. The old patch series can be found in > here [old-series]. > > Note, regarding [2/7] of this patchset, this fix is introduced because > the pcie->ops pointer is not filled in SG2042 PCIe driver. This is not > a must-have parameter, if we use it w/o checking will cause a null > pointer access error during runtime. > > Link: https://lore.kernel.org/linux-riscv/cover.1736923025.git.unicorn_wang@outlook.com/ [old-series] > > Thanks, > Chen > > --- > > Changes in v3: > > This patchset is based on v6.17-rc1. > > Fixed following issues for driver code based on feedbacks from Bjorn Helgaas, > Mingcong Bai, thanks. > > - Fixed the issue when building the driver as a module. Define own pm_ops > inside driver, don't use the ops defined in other built-in drivers. > - Improve .remove() function to properly disable the host. > > Changes in v2: > > This patchset is based on v6.17-rc1. You can simply review or test the > patches at the link [2]. > > Fixed following issues based on feedbacks from Rob Herring, Manivannan Sadhasivam, > Bjorn Helgaas, ALOK TIWARI, thanks. > > - Driver binding: > - Removed vendor-id/device-id from "required" property. > - Improve drivers code: > - Have separated pci_ops for the root bus and child buses. > - Make the driver tristate and as a module. > - Change the configuration name from PCIE_SG2042 to PCIE_SG2042_HOST. > - Removed "Fixes" tag from commit [2/7], since this is not for an existing bug fix. > - Other code cleanups and optimizations > - DT: > - Add PCIe support for SG2042 EVB boards. > > Changes in v1: > > The patch series is based on v6.17-rc1. You can simply review or test the > patches at the link [1]. > > Link: https://lore.kernel.org/linux-riscv/cover.1756344464.git.unicorn_wang@outlook.com/ [1] > Link: https://lore.kernel.org/linux-riscv/cover.1757467895.git.unicorn_wang@outlook.com/ [2] > > --- > > Chen Wang (7): > dt-bindings: pci: Add Sophgo SG2042 PCIe host > PCI: cadence: Check pcie-ops before using it > PCI: sg2042: Add Sophgo SG2042 PCIe driver > riscv: sophgo: dts: add PCIe controllers for SG2042 > riscv: sophgo: dts: enable PCIe for PioneerBox > riscv: sophgo: dts: enable PCIe for SG2042_EVB_V1.X > riscv: sophgo: dts: enable PCIe for SG2042_EVB_V2.0 > > .../bindings/pci/sophgo,sg2042-pcie-host.yaml | 64 ++++++++ > arch/riscv/boot/dts/sophgo/sg2042-evb-v1.dts | 12 ++ > arch/riscv/boot/dts/sophgo/sg2042-evb-v2.dts | 12 ++ > .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 ++ > arch/riscv/boot/dts/sophgo/sg2042.dtsi | 88 +++++++++++ > drivers/pci/controller/cadence/Kconfig | 10 ++ > drivers/pci/controller/cadence/Makefile | 1 + > .../controller/cadence/pcie-cadence-host.c | 2 +- > drivers/pci/controller/cadence/pcie-cadence.c | 4 +- > drivers/pci/controller/cadence/pcie-cadence.h | 6 +- > drivers/pci/controller/cadence/pcie-sg2042.c | 138 ++++++++++++++++++ > 11 files changed, 343 insertions(+), 6 deletions(-) > create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml > create mode 100644 drivers/pci/controller/cadence/pcie-sg2042.c > > > base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585