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to the sg2042 devicetree To: Han Gao , devicetree@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Inochi Amaoto , linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org References: <915bef0530dee6c8bc0ae473837a4bd6786fa4fb.1751698574.git.rabenda.cn@gmail.com> From: Chen Wang In-Reply-To: <915bef0530dee6c8bc0ae473837a4bd6786fa4fb.1751698574.git.rabenda.cn@gmail.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: SG2PR04CA0213.apcprd04.prod.outlook.com (2603:1096:4:187::11) To PNYPR01MB11171.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:2aa::8) X-Microsoft-Original-Message-ID: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: 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X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2025 00:43:06.5675 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-Transport-CrossTenantHeadersStamped: PN3PR01MB6376 On 2025/7/5 15:00, Han Gao wrote: > The sg2042 SoCs support xtheadvector [1] so it can be included in the > devicetree. Also include vlenb for the cpu. And set vlenb=16 [2]. > > This can be tested by passing the "mitigations=off" kernel parameter. > > Link: https://lore.kernel.org/linux-riscv/20241113-xtheadvector-v11-4-236c22791ef9@rivosinc.com/ [1] > Link: https://lore.kernel.org/linux-riscv/aCO44SAoS2kIP61r@ghost/ [2] > > Signed-off-by: Han Gao > Reviewed-by: Inochi Amaoto Reviewed-by: Chen Wang > --- > arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 192 +++++++++++++------- > 1 file changed, 128 insertions(+), 64 deletions(-) > > diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi > index b136b6c4128c..dcc984965b6b 100644 > --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi > +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi > @@ -260,7 +260,8 @@ cpu0: cpu@0 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <0>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -285,7 +286,8 @@ cpu1: cpu@1 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <1>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -310,7 +312,8 @@ cpu2: cpu@2 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <2>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -335,7 +338,8 @@ cpu3: cpu@3 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <3>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -360,7 +364,8 @@ cpu4: cpu@4 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <4>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -385,7 +390,8 @@ cpu5: cpu@5 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <5>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -410,7 +416,8 @@ cpu6: cpu@6 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <6>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -435,7 +442,8 @@ cpu7: cpu@7 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <7>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -460,7 +468,8 @@ cpu8: cpu@8 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <8>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -485,7 +494,8 @@ cpu9: cpu@9 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <9>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -510,7 +520,8 @@ cpu10: cpu@10 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <10>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -535,7 +546,8 @@ cpu11: cpu@11 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <11>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -560,7 +572,8 @@ cpu12: cpu@12 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <12>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -585,7 +598,8 @@ cpu13: cpu@13 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <13>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -610,7 +624,8 @@ cpu14: cpu@14 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <14>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -635,7 +650,8 @@ cpu15: cpu@15 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <15>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -660,7 +676,8 @@ cpu16: cpu@16 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <16>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -685,7 +702,8 @@ cpu17: cpu@17 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <17>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -710,7 +728,8 @@ cpu18: cpu@18 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <18>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -735,7 +754,8 @@ cpu19: cpu@19 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <19>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -760,7 +780,8 @@ cpu20: cpu@20 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <20>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -785,7 +806,8 @@ cpu21: cpu@21 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <21>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -810,7 +832,8 @@ cpu22: cpu@22 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <22>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -835,7 +858,8 @@ cpu23: cpu@23 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <23>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -860,7 +884,8 @@ cpu24: cpu@24 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <24>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -885,7 +910,8 @@ cpu25: cpu@25 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <25>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -910,7 +936,8 @@ cpu26: cpu@26 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <26>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -935,7 +962,8 @@ cpu27: cpu@27 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <27>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -960,7 +988,8 @@ cpu28: cpu@28 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <28>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -985,7 +1014,8 @@ cpu29: cpu@29 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <29>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1010,7 +1040,8 @@ cpu30: cpu@30 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <30>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1035,7 +1066,8 @@ cpu31: cpu@31 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <31>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1060,7 +1092,8 @@ cpu32: cpu@32 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <32>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1085,7 +1118,8 @@ cpu33: cpu@33 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <33>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1110,7 +1144,8 @@ cpu34: cpu@34 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <34>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1135,7 +1170,8 @@ cpu35: cpu@35 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <35>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1160,7 +1196,8 @@ cpu36: cpu@36 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <36>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1185,7 +1222,8 @@ cpu37: cpu@37 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <37>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1210,7 +1248,8 @@ cpu38: cpu@38 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <38>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1235,7 +1274,8 @@ cpu39: cpu@39 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <39>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1260,7 +1300,8 @@ cpu40: cpu@40 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <40>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1285,7 +1326,8 @@ cpu41: cpu@41 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <41>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1310,7 +1352,8 @@ cpu42: cpu@42 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <42>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1335,7 +1378,8 @@ cpu43: cpu@43 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <43>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1360,7 +1404,8 @@ cpu44: cpu@44 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <44>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1385,7 +1430,8 @@ cpu45: cpu@45 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <45>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1410,7 +1456,8 @@ cpu46: cpu@46 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <46>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1435,7 +1482,8 @@ cpu47: cpu@47 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <47>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1460,7 +1508,8 @@ cpu48: cpu@48 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <48>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1485,7 +1534,8 @@ cpu49: cpu@49 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <49>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1510,7 +1560,8 @@ cpu50: cpu@50 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <50>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1535,7 +1586,8 @@ cpu51: cpu@51 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <51>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1560,7 +1612,8 @@ cpu52: cpu@52 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <52>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1585,7 +1638,8 @@ cpu53: cpu@53 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <53>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1610,7 +1664,8 @@ cpu54: cpu@54 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <54>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1635,7 +1690,8 @@ cpu55: cpu@55 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <55>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1660,7 +1716,8 @@ cpu56: cpu@56 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <56>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1685,7 +1742,8 @@ cpu57: cpu@57 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <57>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1710,7 +1768,8 @@ cpu58: cpu@58 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <58>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1735,7 +1794,8 @@ cpu59: cpu@59 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <59>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1760,7 +1820,8 @@ cpu60: cpu@60 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <60>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1785,7 +1846,8 @@ cpu61: cpu@61 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <61>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1810,7 +1872,8 @@ cpu62: cpu@62 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <62>; > i-cache-block-size = <64>; > i-cache-size = <65536>; > @@ -1835,7 +1898,8 @@ cpu63: cpu@63 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "zicntr", "zicsr", "zifencei", > - "zihpm"; > + "zihpm", "xtheadvector"; > + thead,vlenb = <16>; > reg = <63>; > i-cache-block-size = <64>; > i-cache-size = <65536>;