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To: Han Gao , devicetree@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Inochi Amaoto , linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org References: From: Chen Wang In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: SG2PR04CA0209.apcprd04.prod.outlook.com (2603:1096:4:187::12) To PNYPR01MB11171.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:2aa::8) X-Microsoft-Original-Message-ID: <60df61a2-a366-45f8-962e-c07d0cbe49ca@outlook.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PNYPR01MB11171:EE_|PN3PR01MB6376:EE_ X-MS-Office365-Filtering-Correlation-Id: 2074ac83-08f5-452c-ef11-08ddbdb880e0 X-Microsoft-Antispam: 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PN3PR01MB6376 On 2025/7/5 15:00, Han Gao wrote: > sg2042 support Zfh ISA extension [1]. > > Link: https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1737721869472/%E7%8E%84%E9%93%81C910%E4%B8%8EC920R1S6%E7%94%A8%E6%88%B7%E6%89%8B%E5%86%8C%28xrvm%29_20250124.pdf [1] > > Signed-off-by: Han Gao > Reviewed-by: Inochi Amaoto Reviewed-by: Chen Wang > --- > arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 128 ++++++++++---------- > 1 file changed, 64 insertions(+), 64 deletions(-) > > diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi > index f483f62ab0c4..77ded5304272 100644 > --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi > +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi > @@ -260,7 +260,7 @@ cpu0: cpu@0 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <0>; > @@ -287,7 +287,7 @@ cpu1: cpu@1 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <1>; > @@ -314,7 +314,7 @@ cpu2: cpu@2 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <2>; > @@ -341,7 +341,7 @@ cpu3: cpu@3 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <3>; > @@ -368,7 +368,7 @@ cpu4: cpu@4 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <4>; > @@ -395,7 +395,7 @@ cpu5: cpu@5 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <5>; > @@ -422,7 +422,7 @@ cpu6: cpu@6 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <6>; > @@ -449,7 +449,7 @@ cpu7: cpu@7 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <7>; > @@ -476,7 +476,7 @@ cpu8: cpu@8 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <8>; > @@ -503,7 +503,7 @@ cpu9: cpu@9 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <9>; > @@ -530,7 +530,7 @@ cpu10: cpu@10 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <10>; > @@ -557,7 +557,7 @@ cpu11: cpu@11 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <11>; > @@ -584,7 +584,7 @@ cpu12: cpu@12 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <12>; > @@ -611,7 +611,7 @@ cpu13: cpu@13 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <13>; > @@ -638,7 +638,7 @@ cpu14: cpu@14 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <14>; > @@ -665,7 +665,7 @@ cpu15: cpu@15 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <15>; > @@ -692,7 +692,7 @@ cpu16: cpu@16 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <16>; > @@ -719,7 +719,7 @@ cpu17: cpu@17 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <17>; > @@ -746,7 +746,7 @@ cpu18: cpu@18 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <18>; > @@ -773,7 +773,7 @@ cpu19: cpu@19 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <19>; > @@ -800,7 +800,7 @@ cpu20: cpu@20 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <20>; > @@ -827,7 +827,7 @@ cpu21: cpu@21 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <21>; > @@ -854,7 +854,7 @@ cpu22: cpu@22 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <22>; > @@ -881,7 +881,7 @@ cpu23: cpu@23 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <23>; > @@ -908,7 +908,7 @@ cpu24: cpu@24 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <24>; > @@ -935,7 +935,7 @@ cpu25: cpu@25 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <25>; > @@ -962,7 +962,7 @@ cpu26: cpu@26 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <26>; > @@ -989,7 +989,7 @@ cpu27: cpu@27 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <27>; > @@ -1016,7 +1016,7 @@ cpu28: cpu@28 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <28>; > @@ -1043,7 +1043,7 @@ cpu29: cpu@29 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <29>; > @@ -1070,7 +1070,7 @@ cpu30: cpu@30 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <30>; > @@ -1097,7 +1097,7 @@ cpu31: cpu@31 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <31>; > @@ -1124,7 +1124,7 @@ cpu32: cpu@32 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <32>; > @@ -1151,7 +1151,7 @@ cpu33: cpu@33 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <33>; > @@ -1178,7 +1178,7 @@ cpu34: cpu@34 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <34>; > @@ -1205,7 +1205,7 @@ cpu35: cpu@35 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <35>; > @@ -1232,7 +1232,7 @@ cpu36: cpu@36 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <36>; > @@ -1259,7 +1259,7 @@ cpu37: cpu@37 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <37>; > @@ -1286,7 +1286,7 @@ cpu38: cpu@38 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <38>; > @@ -1313,7 +1313,7 @@ cpu39: cpu@39 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <39>; > @@ -1340,7 +1340,7 @@ cpu40: cpu@40 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <40>; > @@ -1367,7 +1367,7 @@ cpu41: cpu@41 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <41>; > @@ -1394,7 +1394,7 @@ cpu42: cpu@42 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <42>; > @@ -1421,7 +1421,7 @@ cpu43: cpu@43 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <43>; > @@ -1448,7 +1448,7 @@ cpu44: cpu@44 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <44>; > @@ -1475,7 +1475,7 @@ cpu45: cpu@45 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <45>; > @@ -1502,7 +1502,7 @@ cpu46: cpu@46 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <46>; > @@ -1529,7 +1529,7 @@ cpu47: cpu@47 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <47>; > @@ -1556,7 +1556,7 @@ cpu48: cpu@48 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <48>; > @@ -1583,7 +1583,7 @@ cpu49: cpu@49 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <49>; > @@ -1610,7 +1610,7 @@ cpu50: cpu@50 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <50>; > @@ -1637,7 +1637,7 @@ cpu51: cpu@51 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <51>; > @@ -1664,7 +1664,7 @@ cpu52: cpu@52 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <52>; > @@ -1691,7 +1691,7 @@ cpu53: cpu@53 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <53>; > @@ -1718,7 +1718,7 @@ cpu54: cpu@54 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <54>; > @@ -1745,7 +1745,7 @@ cpu55: cpu@55 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <55>; > @@ -1772,7 +1772,7 @@ cpu56: cpu@56 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <56>; > @@ -1799,7 +1799,7 @@ cpu57: cpu@57 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <57>; > @@ -1826,7 +1826,7 @@ cpu58: cpu@58 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <58>; > @@ -1853,7 +1853,7 @@ cpu59: cpu@59 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <59>; > @@ -1880,7 +1880,7 @@ cpu60: cpu@60 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <60>; > @@ -1907,7 +1907,7 @@ cpu61: cpu@61 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <61>; > @@ -1934,7 +1934,7 @@ cpu62: cpu@62 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <62>; > @@ -1961,7 +1961,7 @@ cpu63: cpu@63 { > riscv,isa-base = "rv64i"; > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", > "ziccrse", "zicntr", "zicsr", > - "zifencei", "zihpm", > + "zifencei", "zihpm", "zfh", > "xtheadvector"; > thead,vlenb = <16>; > reg = <63>;