From: Chen Wang <unicorn_wang@outlook.com>
To: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Cc: Chen Wang <unicornxw@gmail.com>,
u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu,
arnd@arndb.de, conor+dt@kernel.org, guoren@kernel.org,
inochiama@outlook.com, krzk+dt@kernel.org, palmer@dabbelt.com,
paul.walmsley@sifive.com, robh@kernel.org, tglx@linutronix.de,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, chao.wei@sophgo.com,
xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com
Subject: Re: [PATCH v2 2/3] irqchip: Add the Sophgo SG2042 MSI interrupt controller
Date: Thu, 12 Dec 2024 08:19:17 +0800 [thread overview]
Message-ID: <PNZPR01MB452875A7236D7A2546EC23B4FE3F2@PNZPR01MB4528.INDPRD01.PROD.OUTLOOK.COM> (raw)
In-Reply-To: <0e50f6e5-2442-40e7-8baa-575f139fad37@wanadoo.fr>
On 2024/12/12 0:32, Christophe JAILLET wrote:
> Le 09/12/2024 à 08:12, Chen Wang a écrit :
>> From: Chen Wang <unicorn_wang@outlook.com>
>>
>> Add driver for Sophgo SG2042 MSI interrupt controller.
>>
>> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
>
> ...
>
>> +#define SG2042_VECTOR_MIN 64
>> +#define SG2042_VECTOR_MAX 95
>
> ...
>
>> +static struct irq_chip sg2042_msi_middle_irq_chip = {
>
> const?
Yes, I will add this in next version, thanks.
>
>> + .name = "SG2042 MSI",
>> + .irq_ack = sg2042_msi_irq_ack,
>> + .irq_mask = irq_chip_mask_parent,
>> + .irq_unmask = irq_chip_unmask_parent,
>> +#ifdef CONFIG_SMP
>> + .irq_set_affinity = irq_chip_set_affinity_parent,
>> +#endif
>> + .irq_compose_msi_msg = sg2042_msi_irq_compose_msi_msg,
>> +};
>
> ...
>
>> +static int sg2042_msi_probe(struct platform_device *pdev)
>> +{
>> + struct of_phandle_args args = {};
>> + struct sg2042_msi_data *data;
>> + int ret;
>> +
>> + data = devm_kzalloc(&pdev->dev, sizeof(struct sg2042_msi_data),
>> GFP_KERNEL);
>> + if (!data)
>> + return -ENOMEM;
>> +
>> + data->reg_clr = devm_platform_ioremap_resource_byname(pdev, "clr");
>> + if (IS_ERR(data->reg_clr)) {
>> + dev_err(&pdev->dev, "Failed to map clear register\n");
>> + return PTR_ERR(data->reg_clr);
>> + }
>> +
>> + if (of_property_read_u64(pdev->dev.of_node,
>> "sophgo,msi-doorbell-addr",
>> + &data->doorbell_addr)) {
>> + dev_err(&pdev->dev, "Unable to parse MSI doorbell addr\n");
>> + return -EINVAL;
>> + }
>> +
>> + ret = of_parse_phandle_with_args(pdev->dev.of_node, "msi-ranges",
>> + "#interrupt-cells", 0, &args);
>> + if (ret) {
>> + dev_err(&pdev->dev, "Unable to parse MSI vec base\n");
>> + return ret;
>> + }
>> + data->irq_first = (u32)args.args[0];
>> +
>> + ret = of_property_read_u32_index(pdev->dev.of_node, "msi-ranges",
>> + args.args_count + 1, &data->num_irqs);
>> + if (ret) {
>> + dev_err(&pdev->dev, "Unable to parse MSI vec number\n");
>> + return ret;
>> + }
>> +
>> + if (data->irq_first < SG2042_VECTOR_MIN ||
>> + (data->irq_first + data->num_irqs - 1) > SG2042_VECTOR_MAX) {
>> + dev_err(&pdev->dev, "msi-ranges is incorrect!\n");
>> + return -EINVAL;
>> + }
>> +
>> + mutex_init(&data->msi_map_lock);
>> +
>> + data->msi_map = bitmap_zalloc(data->num_irqs, GFP_KERNEL);
>
> IIUC, num_irqs is between 0 and (SG2042_VECTOR_MAX -
> SG2042_VECTOR_MIN) (maybe + or -1).
> So around 32.
>
> Would it make sence to use DECLARE_BITMAP(msi_map, <correct_size>) in
> sg2042_msi_data to avoid this allocation and an indirection at runtime?
This is also a good choice. I will double check this.
Thanks,
Chen
>
>> + if (!data->msi_map)
>> + return -ENOMEM;
>> +
>> + ret = sg2042_msi_init_domains(data, pdev->dev.of_node);
>> + if (ret)
>> + bitmap_free(data->msi_map);
>> +
>> + return ret;
>> +}
>
> ...
>
> CJ
next prev parent reply other threads:[~2024-12-12 0:19 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-12-09 7:11 [PATCH v2 0/3] irqchip: Add Sophgo SG2042 MSI controller Chen Wang
2024-12-09 7:11 ` [PATCH v2 1/3] dt-bindings: interrupt-controller: Add Sophgo SG2042 MSI Chen Wang
2024-12-09 9:28 ` Krzysztof Kozlowski
2024-12-11 9:08 ` Chen Wang
2024-12-09 7:12 ` [PATCH v2 2/3] irqchip: Add the Sophgo SG2042 MSI interrupt controller Chen Wang
2024-12-09 9:34 ` Krzysztof Kozlowski
2024-12-11 9:10 ` Chen Wang
2024-12-10 7:37 ` kernel test robot
2024-12-10 18:34 ` kernel test robot
2024-12-10 18:44 ` kernel test robot
2024-12-10 23:13 ` Samuel Holland
2024-12-11 9:12 ` Chen Wang
2024-12-11 16:32 ` Christophe JAILLET
2024-12-12 0:19 ` Chen Wang [this message]
2025-01-11 0:45 ` Inochi Amaoto
2025-01-11 1:29 ` Chen Wang
2024-12-09 7:12 ` [PATCH v2 3/3] riscv: sophgo: dts: add msi controller for SG2042 Chen Wang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=PNZPR01MB452875A7236D7A2546EC23B4FE3F2@PNZPR01MB4528.INDPRD01.PROD.OUTLOOK.COM \
--to=unicorn_wang@outlook.com \
--cc=aou@eecs.berkeley.edu \
--cc=arnd@arndb.de \
--cc=chao.wei@sophgo.com \
--cc=christophe.jaillet@wanadoo.fr \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=fengchun.li@sophgo.com \
--cc=guoren@kernel.org \
--cc=inochiama@outlook.com \
--cc=krzk+dt@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh@kernel.org \
--cc=tglx@linutronix.de \
--cc=u.kleine-koenig@baylibre.com \
--cc=unicornxw@gmail.com \
--cc=xiaoguang.xing@sophgo.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®