From: Davide Libenzi <davidel@xmailserver.org>
To: Martin Diehl <lists@mdiehl.de>
Cc: Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: SIS650+CPQ Presario 3045US details ...
Date: Wed, 21 May 2003 15:30:11 -0700 (PDT) [thread overview]
Message-ID: <Pine.LNX.4.55.0305211514400.4369@bigblue.dev.mcafeelabs.com> (raw)
In-Reply-To: <Pine.LNX.4.44.0305212039150.14825-100000@notebook.home.mdiehl.de>
On Wed, 21 May 2003, Martin Diehl wrote:
> On Tue, 20 May 2003, Davide Libenzi wrote:
>
> > Below are reported details about my CPQ Presario 3045US with the new
> > SIS650 chipset. I report how I changed the IRW routing functions, that
> > makes my machine to work fine. I did that completely blindly since I
> > couldn't find specs for the SIS650 chipset (Intel and AMD rulez about
> > docs). As you can see both 0x6* and 0x4* requests are generated by the PCI
> > world.
>
> As already said, taken this way it has the potential to break older SiS
> routing stuff.
You can likely do 's/potential/certainty/' here. The code reported work
for my machine with that chipset, like I said before. Checking the rev-id
will make probably the code to work with both old and new revisions. But
again, w/out docs (and SIS web site sucks at least for this) we're just
trolling here.
- Davide
prev parent reply other threads:[~2003-05-21 22:18 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-05-20 19:09 Davide Libenzi
2003-05-21 19:12 ` Martin Diehl
2003-05-21 22:30 ` Davide Libenzi [this message]
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