Hi,

Am Samstag, 10. Oktober 2026, 14:59:58 Mitteleuropäische Sommerzeit schrieb 
Navid Ghahremani:
> Execute bounded SPI-memory operations through the controller FIFO. Honor
> device and operation clock limits through the CRPM divider and cap the
> validated maximum at 50 MHz.

The registers look identical (though with slightly different names) than the 
quad SPI controller on my machines. I have a more advanced driver here:

https://gitlab.com/stefandoesinger/zx297520-kernel/-/blob/dlink/drivers/spi/
spi-zx.c?ref_type=heads

Please give it a try on your hardware and see if it works.

My driver has optional DMA support, which does allow measurable improvements 
in situations where SPI access and CPU activity happen in parallel (although 
DMA operation is slightly slower than PIO with an otherwise idle CPU) and I 
tuned PIO mode a bit (in particular avoiding redundant fifo size reads).

The qspi driver is a bit down on my FIFO queue (I plan to take care of pinctrl 
and DMA first), but I can speed it up if your board gets to a point where SPI 
can be done reliably first.

On the hardware otherwise, it can also raise IRQs when the read/write FIFOs 
are above/below a certain threshold. That allows PIO mode without constant 
polling. I found that it doesn't have an actual performance advantage over 
polling PIO mode even when pushing the CPU during SPI transfers. DMA mode has 
clear advantages in this regard and I found no need to implement an IRQ driven 
PIO mode. If the performance characteristics on your board are different we can 
reconsider this.