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[178.165.167.132]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a18bf214a1sm243456455e9.7.2026.10.11.06.03.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Oct 2026 06:03:54 -0700 (PDT) From: Stefan =?UTF-8?B?RMO2c2luZ2Vy?= To: linux-arm-kernel@lists.infradead.org, Navid Ghahremani Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, arnd@arndb.de, linux@armlinux.org.uk, robh@kernel.org, krzk@kernel.org, Navid Ghahremani Subject: Re: [PATCH 13/24] PCI: dwc: Add ZTE ZX279128S host controller driver Date: Sun, 11 Oct 2026 15:03:43 +0200 Message-ID: In-Reply-To: <20261010130024.177503-14-ghahramani.navid@gmail.com> References: <20261010130024.177503-1-ghahramani.navid@gmail.com> <20261010130024.177503-14-ghahramani.navid@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; boundary="nextPartayMeA89TTDyMHsX0IsJQmw"; micalg="pgp-sha256"; protocol="application/pgp-signature" --nextPartayMeA89TTDyMHsX0IsJQmw Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8"; protected-headers="v1" From: Stefan =?UTF-8?B?RMO2c2luZ2Vy?= Subject: Re: [PATCH 13/24] PCI: dwc: Add ZTE ZX279128S host controller driver Date: Sun, 11 Oct 2026 15:03:43 +0200 Message-ID: In-Reply-To: <20261010130024.177503-14-ghahramani.navid@gmail.com> MIME-Version: 1.0 Hi, I can't say much about the substance of this patch as I haven't dealt with= =20 PCIe before. What follows are just some gut feeling comments: Am Samstag, 10. Oktober 2026, 14:59:51 Mitteleurop=C3=A4ische Sommerzeit sc= hrieb=20 Navid Ghahremani: > +static int zx279128s_pcie_init_crm(struct zx279128s_pcie *pcie) > +{ =2E.. > + /* Ungate the clocks */ > + ret =3D regmap_write_bits(crm2, CRM2_CLK, port->clk_on, port->clk= _on); > + if (ret) > + return ret; > + fsleep(50); If this is a clock control it would be better to write a clock driver that= =20 manages the crm2 region and exposes a proper clock handle. =46or the phy parts that are part of topcrm: drivers/phy has PCIe PHY drive= rs.=20 Maybe one of them happens to match the hardware registers, although that is= =20 unlikely given that the registers are inside topcrm. Either way adding #phy- cells to topcrm and isolating the phy controls in a phy driver would be bet= ter=20 than having these two syscon controls. By and large the zx279128s_pcie_init_crm has a bad code smell: It looks lik= e=20 an LLM translation of ZTE's code to me without understanding what the=20 registers actually do. --nextPartayMeA89TTDyMHsX0IsJQmw Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part. 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