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b=nzFq9bRhJu87/OaRngp6bUe2pJ/1wfq1CIdb6cY32Yi4XGjaMxwCzkWmGSaCR8JCJ7ulCVH3CwJQUduSe8cvSNUcXFWjr/AMZraabwYKRAe9+TUv1T0QFi1KySZp/saMFduzd6t/aj7MARoqqhmJNXW5UN/HmwbNWBoA73YyVUL8BPxbIR+KhtU/P8RZiCUppdrdnkV8O0/bVbPg/Sn4gUwXvabKqnuNb7BvZCXYEiDiTs6swYzse+zYHZcjWDAeHJuR4BFt3W7Pb9znD6aKRHTcrVyVjEnCy6kDSoMk2JUGVZ9O7CQNLy7kKAgvhk1RDRd1QEfoM8PtwmNB4N0z9g== Received: from SA1PR12MB7199.namprd12.prod.outlook.com (2603:10b6:806:2bc::21) by PH7PR12MB6834.namprd12.prod.outlook.com (2603:10b6:510:1b4::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8534.42; Wed, 26 Mar 2025 08:31:32 +0000 Received: from SA1PR12MB7199.namprd12.prod.outlook.com ([fe80::ae1b:d89a:dfb6:37c2]) by SA1PR12MB7199.namprd12.prod.outlook.com ([fe80::ae1b:d89a:dfb6:37c2%5]) with mapi id 15.20.8534.040; Wed, 26 Mar 2025 08:31:32 +0000 From: Ankit Agrawal To: Catalin Marinas , Jason Gunthorpe CC: Oliver Upton , Marc Zyngier , "joey.gouly@arm.com" , "suzuki.poulose@arm.com" , "yuzenghui@huawei.com" , "will@kernel.org" , "ryan.roberts@arm.com" , "shahuang@redhat.com" , "lpieralisi@kernel.org" , "david@redhat.com" , Aniket Agashe , Neo Jia , Kirti Wankhede , "Tarun Gupta (SW-GPU)" , Vikram Sethi , Andy Currid , Alistair Popple , John Hubbard , Dan Williams , Zhi Wang , Matt Ochs , Uday Dhoke , Dheeraj Nigam , Krishnakant Jaju , "alex.williamson@redhat.com" , "sebastianene@google.com" , "coltonlewis@google.com" , "kevin.tian@intel.com" , "yi.l.liu@intel.com" , "ardb@kernel.org" , "akpm@linux-foundation.org" , "gshan@redhat.com" , "linux-mm@kvack.org" , "ddutile@redhat.com" , "tabba@google.com" , "qperret@google.com" , "seanjc@google.com" , "kvmarm@lists.linux.dev" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH v3 1/1] KVM: arm64: Allow cacheable stage 2 mapping using VMA flags Thread-Topic: [PATCH v3 1/1] KVM: arm64: Allow cacheable stage 2 mapping using VMA flags Thread-Index: AQHbkaduhEbbxySPq0WwO4LU4q6wXLNsQygAgAD/GeCAAIkeAIAAC14ggAFVjACAATjx0YAGtS0AgACvDoCAAOaHAIAANr+AgABucICAAD0IgIAAg/iAgACoeYCAABKYAIAAFAsAgAAouYCACiALVA== Date: Wed, 26 Mar 2025 08:31:32 +0000 Message-ID: References: <8634fcnh0n.wl-maz@kernel.org> <86wmcmn0dp.wl-maz@kernel.org> <20250318125527.GP9311@nvidia.com> <20250318230909.GD9311@nvidia.com> <20250319170429.GK9311@nvidia.com> <20250319192246.GQ9311@nvidia.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; 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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SA1PR12MB7199.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 094c2f20-0bbb-44ec-3870-08dd6c409cc3 X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Mar 2025 08:31:32.0182 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: GwCMl/Ll0xPN/6C3bMPa3HxUmjMhtUaxt/gcyBZ8P/TjrBpFrUFRtTGj3JqHwv5FIIb8zsEi964TbvjOTUSgTA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6834 > On Wed, Mar 19, 2025 at 04:22:46PM -0300, Jason Gunthorpe wrote:=0A= > > On Wed, Mar 19, 2025 at 06:11:02PM +0000, Catalin Marinas wrote:=0A= > > > On Wed, Mar 19, 2025 at 02:04:29PM -0300, Jason Gunthorpe wrote:=0A= > > > > On Wed, Mar 19, 2025 at 12:01:29AM -0700, Oliver Upton wrote:=0A= > > > > > You have a very good point that KVM is broken for cacheable PFNMA= P'd=0A= > > > > > crap since we demote to something non-cacheable, and maybe that= =0A= > > > > > deserves fixing first. Hopefully nobody notices that we've taken = away=0A= > > > > > the toys...=0A= > > > >=0A= > > > > Fixing it is either faulting all access attempts or mapping it=0A= > > > > cachable to the S2 (as this series is trying to do)..=0A= > > >=0A= > > > As I replied earlier, it might be worth doing both - fault on !FWB=0A= > > > hardware (or rather reject the memslot creation), cacheable S2=0A= > > > otherwise.=0A= > >=0A= > > I have no objection, Ankit are you able to make a failure patch?=0A= >=0A= > I'd wait until the KVM maintainers have their say.=0A= > =0A= =0A= Maz, Oliver any thoughts on this? Can we conclude to create this failure=0A= patch in memslot creation?=0A= =0A= =0A= > --=0A= > Catalin=