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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: chipsnmedia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SL2P216MB1246.KORP216.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-Network-Message-Id: b79bb0bd-cbdb-4923-0b60-08dd8ee03473 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 May 2025 09:59:36.0212 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 4d70c8e9-142b-4389-b7f2-fa8a3c68c467 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ySeyP/Gd8ZGPM4kkv83+Vhvpj1KPwCwOsVvr9PmLFTf9N4DAT3czITUNduQ1sXwFFbffDP6xcGd2porWkexIkgJgAsdtf6Jp/1p+xS0oPuY= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PU4P216MB2245 Hi, Krzysztof. Thanks for your feedback. >-----Original Message----- >From: Krzysztof Kozlowski >Sent: Friday, April 25, 2025 7:34 PM >To: Nas Chung >Cc: mchehab@kernel.org; hverkuil@xs4all.nl; sebastian.fricke@collabora.com= ; >robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org; linux- >media@vger.kernel.org; devicetree@vger.kernel.org; linux- >kernel@vger.kernel.org; linux-imx@nxp.com; marex@denx.de; jackson.lee >; lafley.kim >Subject: Re: [PATCH v2 2/8] dt-bindings: media: nxp: Add Wave6 video codec >device > >On Tue, Apr 22, 2025 at 06:31:13PM GMT, Nas Chung wrote: >> Add documents for the Wave6 video codec on NXP i.MX SoCs. >> >> Signed-off-by: Nas Chung >> --- >> .../bindings/media/cnm,wave633c.yaml | 165 ++++++++++++++++++ >> MAINTAINERS | 7 + >> 2 files changed, 172 insertions(+) >> create mode 100644 >Documentation/devicetree/bindings/media/cnm,wave633c.yaml >> >> diff --git a/Documentation/devicetree/bindings/media/cnm,wave633c.yaml >b/Documentation/devicetree/bindings/media/cnm,wave633c.yaml >> new file mode 100644 >> index 000000000000..5bb572e8ca18 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/media/cnm,wave633c.yaml >> @@ -0,0 +1,165 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/media/cnm,wave633c.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Chips&Media Wave6 Series multi-standard codec IP. > >Drop full stop I see, I will remove it. > >> + >> +maintainers: >> + - Nas Chung >> + - Jackson Lee >> + >> +description: >> + The Chips&Media Wave6 codec IP is a multi-standard video >encoder/decoder. >> + On NXP i.MX SoCs, Wave6 codec IP functionality is split between > >... this and ... > >> + the VPU control region and the VPU core region. >> + The VPU control region manages shared resources such as firmware >memory, >> + while the VPU core region provides encoding and decoding >> + capabilities. The VPU core cannot operate independently without >> + the VPU control region. >> + >> +properties: >> + compatible: >> + items: >> + - enum: >> + - nxp,imx95-vpu >> + - const: cnm,wave633c > >... your drivers seem to use soc specific compatible, so I do not see >value in generic compatible. It would have to be good enough alone for >drivers, but it is not. I agree with you. I will drop the generic compatible name and change the yaml file name to nxp,imx95-vpu.yaml. > >> + >> + clocks: >> + items: >> + - description: VPU clock >> + - description: VPU associated block clock >> + >> + clock-names: >> + items: >> + - const: vpu >> + - const: vpublk_wave >> + >> + power-domains: >> + maxItems: 1 >> + description: Main VPU power domain > >Drop description Okay. I will remove the description for power-domains. > >> + >> + "#address-cells": true > >instead const > >> + >> + "#size-cells": true > >const I see, I will change "#address-cells" and "#size-cells" to use const. > >> + >> + ranges: true >> + >> +patternProperties: >> + "^video-core@[0-9a-f]+$": >> + type: object >> + >> + properties: >> + compatible: >> + items: > >Drop items and keep just enum Okay, I will use enum directly. > >> + - enum: >> + - nxp,imx95-vpu-core > >So this is another proof that cnm,wave633c is wrong. How cnm,wave633c >can come with nxp,imx95-vpu-core child? I understand your point. I will address this in my previous comment. Thanks for pointing it out. > >> + >> + reg: >> + maxItems: 1 >> + >> + interrupts: >> + maxItems: 1 >> + >> + required: >> + - compatible >> + - reg >> + - interrupts >> + >> + additionalProperties: false > >Put this immediately after type:object Okay. > >> + >> + "^video-controller@[0-9a-f]+$": >> + type: object > >Same here goes additionalProps. Okay. > >> + >> + properties: >> + compatible: >> + items: >> + - enum: >> + - nxp,imx95-vpu-ctrl >> + >> + reg: >> + maxItems: 1 >> + >> + memory-region: >> + maxItems: 1 >> + >> + power-domains: >> + maxItems: 1 >> + description: Performance power domain >> + >> + '#cooling-cells': > >Keep consistent quotes, either ' or " I see, I will use consistent quoting. > >> + const: 2 >> + >> + sram: >> + $ref: /schemas/types.yaml#/definitions/phandle >> + description: phandle of the SRAM memory region node. >> + >> + required: >> + - compatible >> + - reg >> + - memory-region >> + - power-domains >> + >> + additionalProperties: false >> + >> +required: >> + - compatible >> + - clocks >> + - power-domains >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include >> + #include >> + >> + soc { >> + #address-cells =3D <2>; >> + #size-cells =3D <2>; >> + >> + vpu: video-codec { > >Why this device does not have MMIO? Sorry, but makes little sense and if >you posted and tested your entire DTS you would see why. I initially thought that if the reg property is declared in the child, it would not need to be declared in the parent node. I based this approach on the mediatek,mt8195-jpegenc.yaml binding, where the parent node does not include MMIO. But, if this structure is problematic, I will address it in patch v3. > >Can we see the entire DTS? Sure ! Below is the cnm.wave633c.example.dts file created from dt_binding_check. /dts-v1/; /plugin/; // silence any missing phandle references /{ compatible =3D "foo"; model =3D "foo"; #address-cells =3D <1>; #size-cells =3D <1>; example-0 { #address-cells =3D <1>; #size-cells =3D <1>; =20 interrupt-parent =3D <&fake_intc0>; fake_intc0: fake-interrupt-controller { interrupt-controller; #interrupt-cells =3D < 3 >; }; #include #include =20 soc { #address-cells =3D <2>; #size-cells =3D <2>; =20 vpu: video-codec { compatible =3D "nxp,imx95-vpu", "cnm,wave633c"; clocks =3D <&scmi_clk 115>, <&vpu_blk_ctrl IMX95_CLK_VPUBLK_WAVE>; clock-names =3D "vpu", "vpublk_wave"; power-domains =3D <&scmi_devpd 21>; #address-cells =3D <2>; #size-cells =3D <2>; ranges; =20 vpucore0: video-core@4c480000 { compatible =3D "nxp,imx95-vpu-core"; reg =3D <0x0 0x4c480000 0x0 0x10000>; interrupts =3D ; }; =20 vpucore1: video-core@4c490000 { compatible =3D "nxp,imx95-vpu-core"; reg =3D <0x0 0x4c490000 0x0 0x10000>; interrupts =3D ; }; =20 vpucore2: video-core@4c4a0000 { compatible =3D "nxp,imx95-vpu-core"; reg =3D <0x0 0x4c4a0000 0x0 0x10000>; interrupts =3D ; }; =20 vpucore3: video-core@4c4b0000 { compatible =3D "nxp,imx95-vpu-core"; reg =3D <0x0 0x4c4b0000 0x0 0x10000>; interrupts =3D ; }; =20 vpuctrl: video-controller@4c4c0000 { compatible =3D "nxp,imx95-vpu-ctrl"; reg =3D <0x0 0x4c4c0000 0x0 0x10000>; memory-region =3D <&vpu_boot>; power-domains =3D <&scmi_perf 10>; #cooling-cells =3D <2>; sram =3D <&sram1>; }; }; }; }; }; > >Best regards, >Krzysztof