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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: chipsnmedia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SL2P216MB1246.KORP216.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-Network-Message-Id: 78491408-e26f-404d-1174-08dd9778b1db X-MS-Exchange-CrossTenant-originalarrivaltime: 20 May 2025 08:31:19.2194 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 4d70c8e9-142b-4389-b7f2-fa8a3c68c467 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: TgCsp/JHwwFNfmTnBGNUBMYQ3/rirScXfjw6/s3iVm5T3OMfKoKl2q1NRwsDQVXQNDtUUybbyNJIhs3O6hiRojIAvclZW2Ov++wuhlMQCJs= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SE1P216MB2242 Hi, Krzysztof. >-----Original Message----- >From: Krzysztof Kozlowski >Sent: Tuesday, May 20, 2025 3:27 PM >To: Nas Chung >Cc: mchehab@kernel.org; hverkuil@xs4all.nl; robh@kernel.org; >krzk+dt@kernel.org; conor+dt@kernel.org; linux-media@vger.kernel.org; >devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-imx@nxp.co= m; >marex@denx.de; jackson.lee ; lafley.kim > >Subject: Re: [PATCH v2 2/8] dt-bindings: media: nxp: Add Wave6 video codec >device > >On 19/05/2025 07:08, Nas Chung wrote: >> Hi, Krzysztof. >> >>> -----Original Message----- >>> From: Krzysztof Kozlowski >>> Sent: Friday, May 16, 2025 9:56 PM >>> To: Nas Chung >>> Cc: mchehab@kernel.org; hverkuil@xs4all.nl; >sebastian.fricke@collabora.com; >>> robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org; linux- >>> media@vger.kernel.org; devicetree@vger.kernel.org; linux- >>> kernel@vger.kernel.org; linux-imx@nxp.com; marex@denx.de; jackson.lee >>> ; lafley.kim >>> Subject: Re: [PATCH v2 2/8] dt-bindings: media: nxp: Add Wave6 video >codec >>> device >>> >>> On 13/05/2025 09:39, Nas Chung wrote: >>>>> >>>>> All of above are wrong for the SoC... >>>>> >>>>>> >>>>>> #include >>>>>> #include >>>>>> >>>>>> soc { >>>>>> #address-cells =3D <2>; >>>>>> #size-cells =3D <2>; >>>>>> >>>>>> vpu: video-codec { >>>>>> compatible =3D "nxp,imx95-vpu", "cnm,wave633c"; >>>>> >>>>> What does this device represent? It is not "ctrl", because you made >ctrl >>>>> separate device node. Your binding description suggests that is the >VPU >>>>> control region. >>>> >>>> My intention was to represent the MMIO VPU device, which includes >>>> both the core and control nodes. >>> >>> Then what is the VPU device if not CTRL? What is the CTRL device? >> >> The VPU device represents the entire VPU hardware block, >> which includes 1 CTRL component(node) and 4 CORE components(nodes). > >What is entire VPU hardware block? I understand your point. The entire VPU hardware block cannot be considered a device on its own. > >> >> The CTRL device represents the VCPU, a 32-bit processor embedded within >the >> VPU hardware block. This VCPU is responsible for executing the VPU >firmware. >> The CTRL device is in charge of tasks such as firmware booting, power >management >> (sleep and wakeup command), and managing memory regions that are >exclusively >> accessed by the firmware. > >This sounds like CTRL is responsible for entire VPU block. What are the >tasks of VPU block then? What are its registers? What is that device >exactly doing? You're right - the VPU block itself does not have any dedicated registers or functionality beyond what is handled by the CTRL and CORE components. Therefore, it cannot be clearly defined as a device. > >You keep repeating the same, so my initial idea - CTRL is not a separate >block - still stands. Can you have more CTRL blocks than one? No, there is only one CTRL block in the hardware. I agree with your view that the CTRL node should be treated as the top-leve= l device node, with the COREs as its child nodes. I will revise the bindings accordingly and reflect this structure in v3. Thank you for the detailed feedback and clarification. Thanks. Nas. > >Best regards, >Krzysztof