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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: chipsnmedia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SL2P216MB2441.KORP216.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-Network-Message-Id: 37fba83e-655c-4de1-601b-08ded25b2b11 X-MS-Exchange-CrossTenant-originalarrivaltime: 25 Jun 2026 01:43:33.9556 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 4d70c8e9-142b-4389-b7f2-fa8a3c68c467 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: NlGqkFGeuK2Tp9/PJZwnOQtBDtMdYQE79fZr+S10l1qmPTJWSt6XNK8p3QXJHyCoXDPeOMeI5QE17yTEGQQWCgiXwQoxnH/TaKrYmAWKR00= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SE2P216MB890387 Hi, Conor. >-----Original Message----- >From: Conor Dooley >Sent: Thursday, June 25, 2026 1:42 AM >To: Nas Chung >Cc: mchehab@kernel.org; hverkuil@xs4all.nl; robh@kernel.org; >krzk+dt@kernel.org; conor+dt@kernel.org; shawnguo@kernel.org; >s.hauer@pengutronix.de; linux-media@vger.kernel.org; >devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-imx@nxp.co= m; >linux-arm-kernel@lists.infradead.org; jackson.lee >; lafley.kim ; >marek.vasut@mailbox.org >Subject: Re: [PATCH v6 2/9] dt-bindings: media: nxp: Add Wave6 video codec >device > >On Wed, Jun 24, 2026 at 04:20:36PM +0900, Nas Chung wrote: >> Add documentation for the Chips&Media Wave6 video codec on NXP i.MX SoCs= . >> >> The hardware contains one control register region and four interface >> register regions for a shared video processing engine. The control regio= n >> manages shared resources such as firmware memory, while each interface >> region has its own MMIO range and interrupt. >> >> The control region and each interface region are distinct DMA requesters >> and can be associated with separate IOMMU stream IDs. Represent the >> control region as the parent node and the interface register regions as >> child nodes to describe these resources. >> >> Signed-off-by: Nas Chung >> --- >> .../bindings/media/nxp,imx95-vpu.yaml | 163 ++++++++++++++++++ >> MAINTAINERS | 7 + >> 2 files changed, 170 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/media/nxp,imx95- >vpu.yaml >> >> diff --git a/Documentation/devicetree/bindings/media/nxp,imx95-vpu.yaml >b/Documentation/devicetree/bindings/media/nxp,imx95-vpu.yaml >> new file mode 100644 >> index 000000000000..9a5ca53e15a3 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/media/nxp,imx95-vpu.yaml >> @@ -0,0 +1,163 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/media/nxp,imx95-vpu.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Chips&Media Wave6 Series multi-standard codec IP on NXP i.MX SoC= s >> + >> +maintainers: >> + - Nas Chung >> + - Jackson Lee >> + >> +description: >> + The Chips&Media Wave6 codec IP is a multi-standard video >encoder/decoder. >> + On NXP i.MX SoCs, the Wave6 codec IP exposes one control register >region and >> + four interface register regions for a shared video processing engine. >> + The parent node describes the control region, which has its own MMIO >range and >> + manages shared resources such as firmware memory. The child nodes >describe the >> + interface register regions. Each interface region has its own MMIO >range and >> + interrupt. >> + The control region and the interface regions are distinct DMA >requesters. >> + The control region and each interface region can be associated with >separate >> + IOMMU stream IDs, allowing DMA isolation between them. >> + >> +properties: >> + compatible: >> + enum: >> + - nxp,imx95-vpu >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + items: >> + - description: VPU core clock >> + - description: VPU associated block clock >> + >> + clock-names: >> + items: >> + - const: core >> + - const: vpublk >> + >> + power-domains: >> + items: >> + - description: Main VPU power domain >> + - description: Performance power domain >> + >> + power-domain-names: >> + items: >> + - const: vpu >> + - const: perf >> + >> + memory-region: >> + maxItems: 1 >> + >> + sram: >> + $ref: /schemas/types.yaml#/definitions/phandle >> + description: >> + phandle to the SRAM node used to store reference data, reducing D= MA >> + memory bandwidth. >> + >> + iommus: >> + maxItems: 1 >> + >> + "#cooling-cells": >> + const: 2 >> + >> + "#address-cells": >> + const: 2 >> + >> + "#size-cells": >> + const: 2 >> + >> + ranges: true >> + >> +patternProperties: >> + "^interface@[0-9a-f]+$": > >I have to wonder if this interface business is required at all. >Why can this not go into the parent, with each region fetchable via >reg-names, interrupt-names and iommu-names? Thanks for your feedback. I did try the flat model, but the blocker is the IOMMU. The control region and four interface regions are independent DMA requester= s with distinct stream IDs, and each interface can be assigned to a different= VM, driving the video core with its own isolated memory. If all stream IDs are listed under the parent's iommus, they bind to a single device and share one domain, so the isolation is lost. This is the main reason I added the interface nodes. Thanks. Nas. > >Cheers, >Conor. > >> + type: object >> + description: >> + An interface register region within the Chips&Media Wave6 codec I= P. >> + Each region has its own MMIO range and interrupt and can be >associated >> + with a separate IOMMU stream ID for DMA isolation. >> + additionalProperties: false >> + >> + properties: >> + reg: >> + maxItems: 1 >> + >> + interrupts: >> + maxItems: 1 >> + >> + iommus: >> + maxItems: 1 >> + >> + required: >> + - reg >> + - interrupts >> + >> +required: >> + - compatible >> + - reg >> + - clocks >> + - clock-names >> + - power-domains >> + - power-domain-names >> + - memory-region >> + - "#address-cells" >> + - "#size-cells" >> + - ranges >> + >> +additionalProperties: false >> + >> +examples: >> + - | >> + #include >> + #include >> + >> + soc { >> + #address-cells =3D <2>; >> + #size-cells =3D <2>; >> + >> + video-codec@4c4c0000 { >> + compatible =3D "nxp,imx95-vpu"; >> + reg =3D <0x0 0x4c4c0000 0x0 0x10000>; >> + clocks =3D <&scmi_clk 115>, >> + <&vpu_blk_ctrl IMX95_CLK_VPUBLK_WAVE>; >> + clock-names =3D "core", "vpublk"; >> + power-domains =3D <&scmi_devpd 21>, >> + <&scmi_perf 10>; >> + power-domain-names =3D "vpu", "perf"; >> + memory-region =3D <&vpu_boot>; >> + sram =3D <&sram1>; >> + iommus =3D <&smmu 0x32>; >> + #cooling-cells =3D <2>; >> + #address-cells =3D <2>; >> + #size-cells =3D <2>; >> + ranges; >> + >> + interface@4c480000 { >> + reg =3D <0x0 0x4c480000 0x0 0x10000>; >> + interrupts =3D ; >> + iommus =3D <&smmu 0x33>; >> + }; >> + >> + interface@4c490000 { >> + reg =3D <0x0 0x4c490000 0x0 0x10000>; >> + interrupts =3D ; >> + iommus =3D <&smmu 0x34>; >> + }; >> + >> + interface@4c4a0000 { >> + reg =3D <0x0 0x4c4a0000 0x0 0x10000>; >> + interrupts =3D ; >> + iommus =3D <&smmu 0x35>; >> + }; >> + >> + interface@4c4b0000 { >> + reg =3D <0x0 0x4c4b0000 0x0 0x10000>; >> + interrupts =3D ; >> + iommus =3D <&smmu 0x36>; >> + }; >> + }; >> + }; >> diff --git a/MAINTAINERS b/MAINTAINERS >> index efbf808063e5..77ea3a1a966b 100644 >> --- a/MAINTAINERS >> +++ b/MAINTAINERS >> @@ -28688,6 +28688,13 @@ S: Maintained >> F: Documentation/devicetree/bindings/media/cnm,wave521c.yaml >> F: drivers/media/platform/chips-media/wave5/ >> >> +WAVE6 VPU CODEC DRIVER >> +M: Nas Chung >> +M: Jackson Lee >> +L: linux-media@vger.kernel.org >> +S: Maintained >> +F: Documentation/devicetree/bindings/media/nxp,imx95-vpu.yaml >> + >> WHISKEYCOVE PMIC GPIO DRIVER >> M: Kuppuswamy Sathyanarayanan > >> L: linux-gpio@vger.kernel.org >> -- >> 2.31.1 >>