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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: chipsnmedia.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SL2P216MB2441.KORP216.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-Network-Message-Id: f3111610-580b-47d4-1f3a-08ded72fa6f1 X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Jul 2026 05:14:39.7034 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 4d70c8e9-142b-4389-b7f2-fa8a3c68c467 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 2uYj/QMBJQ+OPjgxb0nY/YmQUjYYheKVhkZXSdRtfghEnVl3U2GIE6MSmpOFXkb0aXw9xXFARjEPL6ZoU8feA5SuuWpNY5HyzBDS6cSzb3A= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SEWP216MB3107 Hi, Rob. >-----Original Message----- >From: Rob Herring >Sent: Wednesday, July 1, 2026 1:14 AM > >On Wed, Jun 24, 2026 at 04:20:36PM +0900, Nas Chung wrote: >> Add documentation for the Chips&Media Wave6 video codec on NXP i.MX SoCs= . >> >> The hardware contains one control register region and four interface >> register regions for a shared video processing engine. The control regio= n >> manages shared resources such as firmware memory, while each interface >> region has its own MMIO range and interrupt. >> >> The control region and each interface region are distinct DMA requesters >> and can be associated with separate IOMMU stream IDs. Represent the >> control region as the parent node and the interface register regions as >> child nodes to describe these resources. >> >> Signed-off-by: Nas Chung >> --- >> .../bindings/media/nxp,imx95-vpu.yaml | 163 ++++++++++++++++++ >> MAINTAINERS | 7 + >> 2 files changed, 170 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/media/nxp,imx95- >vpu.yaml >> >> diff --git a/Documentation/devicetree/bindings/media/nxp,imx95-vpu.yaml >b/Documentation/devicetree/bindings/media/nxp,imx95-vpu.yaml >> new file mode 100644 >> index 000000000000..9a5ca53e15a3 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/media/nxp,imx95-vpu.yaml >> @@ -0,0 +1,163 @@ >> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/media/nxp,imx95-vpu.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Chips&Media Wave6 Series multi-standard codec IP on NXP i.MX SoC= s >> + >> +maintainers: >> + - Nas Chung >> + - Jackson Lee >> + >> +description: >> + The Chips&Media Wave6 codec IP is a multi-standard video >encoder/decoder. >> + On NXP i.MX SoCs, the Wave6 codec IP exposes one control register >region and >> + four interface register regions for a shared video processing engine. >> + The parent node describes the control region, which has its own MMIO >range and >> + manages shared resources such as firmware memory. The child nodes >describe the >> + interface register regions. Each interface region has its own MMIO >range and >> + interrupt. >> + The control region and the interface regions are distinct DMA >requesters. >> + The control region and each interface region can be associated with >separate >> + IOMMU stream IDs, allowing DMA isolation between them. >> + >> +properties: >> + compatible: >> + enum: >> + - nxp,imx95-vpu >> + >> + reg: >> + maxItems: 1 >> + >> + clocks: >> + items: >> + - description: VPU core clock >> + - description: VPU associated block clock >> + >> + clock-names: >> + items: >> + - const: core >> + - const: vpublk >> + >> + power-domains: >> + items: >> + - description: Main VPU power domain >> + - description: Performance power domain >> + >> + power-domain-names: >> + items: >> + - const: vpu >> + - const: perf >> + >> + memory-region: >> + maxItems: 1 >> + >> + sram: >> + $ref: /schemas/types.yaml#/definitions/phandle > >Already has a type. You just need to define how many phandles (maxItems: 1= ). Thanks for your feedback. I see sram-consumer.yaml provides the type now. I'll address this in v7. > >> + description: >> + phandle to the SRAM node used to store reference data, reducing D= MA >> + memory bandwidth. > >Drop 'phandle to the SRAM node' Okay. Thanks. Nas. > >Rob