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Fri, 12 Jun 2026 15:51:51 +0000 Received: from SN6PR02MB4157.namprd02.prod.outlook.com ([fe80::900:1ccf:2b1e:52b6]) by SN6PR02MB4157.namprd02.prod.outlook.com ([fe80::900:1ccf:2b1e:52b6%3]) with mapi id 15.21.0113.013; Fri, 12 Jun 2026 15:51:51 +0000 From: Michael Kelley To: Jinjie Ruan , "catalin.marinas@arm.com" , "will@kernel.org" , "tsbogend@alpha.franken.de" , "pjw@kernel.org" , "palmer@dabbelt.com" , "aou@eecs.berkeley.edu" , "alex@ghiti.fr" , "tglx@kernel.org" , "mingo@redhat.com" , "bp@alien8.de" , "dave.hansen@linux.intel.com" , "hpa@zytor.com" , "peterz@infradead.org" , "kees@kernel.org" , "nathan@kernel.org" , "linusw@kernel.org" , "ojeda@kernel.org" , "david.kaplan@amd.com" , "lukas.bulwahn@redhat.com" , "ryan.roberts@arm.com" , "maz@kernel.org" , "timothy.hayes@arm.com" , "lpieralisi@kernel.org" , "thuth@redhat.com" , "oupton@kernel.org" , "yeoreum.yun@arm.com" , "miko.lenczewski@arm.com" , "broonie@kernel.org" , "kevin.brodsky@arm.com" , "james.clark@linaro.org" , "tabba@google.com" , "mrigendra.chaubey@gmail.com" , "arnd@arndb.de" , "anshuman.khandual@arm.com" , "x86@kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-mips@vger.kernel.org" , "linux-riscv@lists.infradead.org" Subject: RE: [PATCH RFC 0/3] arm64: Add HOTPLUG_PARALLEL support for secondary CPUs Thread-Topic: [PATCH RFC 0/3] arm64: Add HOTPLUG_PARALLEL support for secondary CPUs Thread-Index: AQKOA8X39m4tY91Ji20k4ddnJ9pPpLTY/WbA Date: Fri, 12 Jun 2026 15:51:51 +0000 Message-ID: References: <20260611133809.3854977-1-ruanjinjie@huawei.com> In-Reply-To: <20260611133809.3854977-1-ruanjinjie@huawei.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: SN6PR02MB4157:EE_|CH2PR02MB7078:EE_ x-ms-office365-filtering-correlation-id: 9157891e-a0e6-4662-f432-08dec89a84f8 x-microsoft-antispam: BCL:0;ARA:14566002|19101099003|15080799012|19110799012|31061999003|8060799015|13091999003|8062599012|37011999003|51005399006|3412199025|440099028|102099032|40105399003|19061999003; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN6PR02MB4157.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-CrossTenant-Network-Message-Id: 9157891e-a0e6-4662-f432-08dec89a84f8 X-MS-Exchange-CrossTenant-originalarrivaltime: 12 Jun 2026 15:51:51.4152 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-CrossTenant-rms-persistedconsumerorg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR02MB7078 From: Jinjie Ruan Sent: Thursday, June 11, 2026 6:3= 8 AM >=20 > Support for parallel secondary CPU bringup is already utilized by x86, > MIPS, and RISC-V. This patch brings this capability to the arm64 > architecture. >=20 > Introduce CONFIG_PARALLEL_SMT_PRIMARY_FIRST to avoid primary SMT threads > to boot first constraint. >=20 > And Add a 'cpu' parameter to update_cpu_boot_status() to allow updating t= he > boot status at a per-CPU granularity during parallel bringup. >=20 > Rework the global `secondary_data` accessed during early boot into > a per-CPU array. This array maps logical CPU IDs to MPIDR_EL1 values, > enabling the early boot code in head.S to resolve each secondary CPU's > logical ID concurrently. I tested the series on an ARM64 VM running on Hyper-V in the Azure cloud. Tested with 16 vCPUs in the VM and with 96 vCPUs in the VM. No issues. I mainly wanted to make sure nothing expected happened with Hyper-V as the host. With 96 vCPUs, the secondary CPU startup time drops from ~140 milliseconds to ~130 milliseconds. That improvement is not as dramatic as you saw on QEMU, so I presume the difference is due to the hypervisor implementation of the PSCI calls. Tested-by: Michael Kelley >=20 > Jinjie Ruan (3): > cpu/hotplug: Introduce CONFIG_PARALLEL_SMT_PRIMARY_FIRST > arm64: smp: Pass CPU ID to update_cpu_boot_status() > arm64: Add HOTPLUG_PARALLEL support for secondary CPUs >=20 > arch/Kconfig | 4 ++++ > arch/arm64/Kconfig | 1 + > arch/arm64/include/asm/smp.h | 14 +++++++++++--- > arch/arm64/kernel/cpufeature.c | 2 +- > arch/arm64/kernel/head.S | 23 ++++++++++++++++++++++ > arch/arm64/kernel/smp.c | 35 ++++++++++++++++++++++++++++++---- > arch/arm64/mm/context.c | 2 +- > arch/mips/Kconfig | 1 + > arch/riscv/Kconfig | 1 + > arch/x86/Kconfig | 1 + > kernel/cpu.c | 6 +++++- > 11 files changed, 80 insertions(+), 10 deletions(-) >=20 > -- > 2.34.1 >=20