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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , "netdev@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "open list:Hyper-V/Azure CORE AND DRIVERS" CC: Manivannan Sadhasivam , Bjorn Helgaas Subject: RE: [PATCH for-netdev v2 2/2] PCI: hv: Switch to msi_create_parent_irq_domain() Thread-Topic: [PATCH for-netdev v2 2/2] PCI: hv: Switch to msi_create_parent_irq_domain() Thread-Index: AQHb7xf/A8zJRWFEyk2mZWYCCrZaYbQm/Dxw Date: Mon, 7 Jul 2025 18:49:02 +0000 Message-ID: References: <7b99cca47b41dacc9a82b96093935eab07cac43a.1751875853.git.namcao@linutronix.de> In-Reply-To: <7b99cca47b41dacc9a82b96093935eab07cac43a.1751875853.git.namcao@linutronix.de> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: SN6PR02MB4157:EE_|MW4PR02MB7281:EE_ x-ms-office365-filtering-correlation-id: 6ff331ba-7351-4b1a-249b-08ddbd86f12a x-ms-exchange-slblob-mailprops: dx7TrgQSB6eQGC/G7Dawllljy95FzHWbT6yKBgT772Qf4EbSIkMHVgZofVfovKAhCHDZdJTGdkTPxGHPw2KhmPOxgYuf/Kri8QzaqRVzrPAHXF2gAas6rQbRNJVAS1b53DHY3uY7252gSXlu8F5+/LxErT9+AEOo/lpw9xkvZsjjdiRxLTVURClwAVWzMUmPRUCWjRM89wxtQBZz2Pscvh+RreN1ETeXPc/XfmEOQv2PfrxrZdwlueiJ45M2PRDQzVRyN/taY88KgmXEC7v5tiKJVmfUhqMsztCcdypVRHTVUf1EkmZduuKMrC3ydb7+jxS1WjTyzswSv4JkdBkNPrHUFeckU/a+SwnavW6+WVVoOcwO6q29AFS/osfDwv2Lx2isnRxwi1gIlm6YigCHBRRwRAV8IWmCJQmKMvW1Y/dXplU2k/aFqQ990UsUNRIsKdfSZDDGZ5fUjs+BfuS4Bw1r994yJ0REdkIVl0KMJS3q5s25Kl2uBToN2w5ojsG5sxn0qiorQznYVaD1yq1N1AFEQwRIsI5hqJjLGsvC1ow1ID2+ME0kneUXdcqA5HVMv4v6px5w3vaB6aQ57Hk7+cnKOOYzpp2Xt3PP0y2pocFT2hMWSbP8k8LONixKFrFZtEhRjHWMG1JvTW/vVwJ70Eb0KRl4+y6EFOv8+hwrLjRwqVQc+G4WyewDjRTz+Rm0cghtWp6mwY9x62KWQq4kNye5EGF8JbfVAV+ILHsJOgAIyC7zRa6lVO8sEm/hvjrg+p45JqFbm5A= x-microsoft-antispam: BCL:0;ARA:14566002|8060799012|41001999006|461199028|8062599008|13031999003|40105399003|52005399003|3412199025|440099028|19111999003|12091999003|102099032; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN6PR02MB4157.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-CrossTenant-Network-Message-Id: 6ff331ba-7351-4b1a-249b-08ddbd86f12a X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Jul 2025 18:49:02.5189 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-CrossTenant-rms-persistedconsumerorg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR02MB7281 From: Nam Cao Sent: Monday, July 7, 2025 1:20 AM >=20 > Move away from the legacy MSI domain setup, switch to use > msi_create_parent_irq_domain(). >=20 > While doing the conversion, I noticed that hv_compose_msi_msg() is doing > more than it is supposed to (composing message). This function also > allocates and populates struct tran_int_desc, which should be done in > hv_pcie_domain_alloc() instead. It works, but it is not the correct desig= n. > However, I have no hardware to test such change, therefore I leave a TODO > note. >=20 > Acked-by: Bjorn Helgaas > Reviewed-by: Thomas Gleixner > Signed-off-by: Nam Cao [Adding linux-hyperv@vger.kernel.org so that the Linux on Hyper-V folks have visibility.] This all looks good to me now. Thanks for the additional explanation of the TODO. I understand what you are suggesting. Moving the interaction with the Hyper-V host into hv_pcie_domain_alloc() has additional appeal because it should eliminate the need for the ugly polling for a VMBus response. However, I'm unlikely to be the person implementing the TODO. hv_compose_msi_msg() is a real beast of a function, and I lack access to hardware to fully test the move, particularly a device that does multi MSI. I don't think such a device is available in a VM in the Azure public cloud. I've tested this patch in an Azure VM that has a MANA NIC. The MANA driver has updates in linux-next to use MSIX dynamic allocation, and that dynamic allocation appears to work correctly with this patch. My testing included unbind and rebind the driver several times so that the full round-trip is tested. Reviewed-by: Michael Kelley Tested-by: Michael Kelley > --- > v2: > - rebase onto netdev/next > - clarify the TODO note > - fixup arm64 > - Add HV_MSI_CHIP_FLAGS macro and reduce the amount of #ifdef > --- > drivers/pci/Kconfig | 1 + > drivers/pci/controller/pci-hyperv.c | 111 +++++++++++++++++++++------- > 2 files changed, 84 insertions(+), 28 deletions(-) >=20 > diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig > index 9c0e4aaf4e8c..9a249c65aedc 100644 > --- a/drivers/pci/Kconfig > +++ b/drivers/pci/Kconfig > @@ -223,6 +223,7 @@ config PCI_HYPERV > tristate "Hyper-V PCI Frontend" > depends on ((X86 && X86_64) || ARM64) && HYPERV && PCI_MSI && SYSFS > select PCI_HYPERV_INTERFACE > + select IRQ_MSI_LIB > help > The PCI device frontend driver allows the kernel to import arbitrary > PCI devices from a PCI backend to support PCI driver domains. > diff --git a/drivers/pci/controller/pci-hyperv.c b/drivers/pci/controller= /pci-hyperv.c > index 86ca041bf74a..ebe39218479a 100644 > --- a/drivers/pci/controller/pci-hyperv.c > +++ b/drivers/pci/controller/pci-hyperv.c > @@ -44,6 +44,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -508,7 +509,6 @@ struct hv_pcibus_device { > struct list_head children; > struct list_head dr_list; >=20 > - struct msi_domain_info msi_info; > struct irq_domain *irq_domain; >=20 > struct workqueue_struct *wq; > @@ -576,9 +576,8 @@ struct hv_pci_compl { > static void hv_pci_onchannelcallback(void *context); >=20 > #ifdef CONFIG_X86 > -#define DELIVERY_MODE APIC_DELIVERY_MODE_FIXED > -#define FLOW_HANDLER handle_edge_irq > -#define FLOW_NAME "edge" > +#define DELIVERY_MODE APIC_DELIVERY_MODE_FIXED > +#define HV_MSI_CHIP_FLAGS MSI_CHIP_FLAG_SET_ACK >=20 > static int hv_pci_irqchip_init(void) > { > @@ -723,8 +722,7 @@ static void hv_arch_irq_unmask(struct irq_data *data) > #define HV_PCI_MSI_SPI_START 64 > #define HV_PCI_MSI_SPI_NR (1020 - HV_PCI_MSI_SPI_START) > #define DELIVERY_MODE 0 > -#define FLOW_HANDLER NULL > -#define FLOW_NAME NULL > +#define HV_MSI_CHIP_FLAGS MSI_CHIP_FLAG_SET_EOI > #define hv_msi_prepare NULL >=20 > struct hv_pci_chip_data { > @@ -1687,7 +1685,7 @@ static void hv_msi_free(struct irq_domain *domain, = struct > msi_domain_info *info, > struct msi_desc *msi =3D irq_data_get_msi_desc(irq_data); >=20 > pdev =3D msi_desc_to_pci_dev(msi); > - hbus =3D info->data; > + hbus =3D domain->host_data; > int_desc =3D irq_data_get_irq_chip_data(irq_data); > if (!int_desc) > return; > @@ -1705,7 +1703,6 @@ static void hv_msi_free(struct irq_domain *domain, = struct > msi_domain_info *info, >=20 > static void hv_irq_mask(struct irq_data *data) > { > - pci_msi_mask_irq(data); > if (data->parent_data->chip->irq_mask) > irq_chip_mask_parent(data); > } > @@ -1716,7 +1713,6 @@ static void hv_irq_unmask(struct irq_data *data) >=20 > if (data->parent_data->chip->irq_unmask) > irq_chip_unmask_parent(data); > - pci_msi_unmask_irq(data); > } >=20 > struct compose_comp_ctxt { > @@ -2101,25 +2097,87 @@ static void hv_compose_msi_msg(struct irq_data *d= ata, struct msi_msg *msg) > msg->data =3D 0; > } >=20 > +static bool hv_pcie_init_dev_msi_info(struct device *dev, struct irq_dom= ain *domain, > + struct irq_domain *real_parent, struct msi_domain_info *info) > +{ > + struct irq_chip *chip =3D info->chip; > + > + if (!msi_lib_init_dev_msi_info(dev, domain, real_parent, info)) > + return false; > + > + info->ops->msi_prepare =3D hv_msi_prepare; > + > + chip->irq_set_affinity =3D irq_chip_set_affinity_parent; > + > + if (IS_ENABLED(CONFIG_X86)) > + chip->flags |=3D IRQCHIP_MOVE_DEFERRED; > + > + return true; > +} > + > +#define HV_PCIE_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ > + MSI_FLAG_USE_DEF_CHIP_OPS | \ > + MSI_FLAG_PCI_MSI_MASK_PARENT) > +#define HV_PCIE_MSI_FLAGS_SUPPORTED (MSI_FLAG_MULTI_PCI_MSI | \ > + MSI_FLAG_PCI_MSIX | \ > + MSI_FLAG_PCI_MSIX_ALLOC_DYN | \ > + MSI_GENERIC_FLAGS_MASK) > + > +static const struct msi_parent_ops hv_pcie_msi_parent_ops =3D { > + .required_flags =3D HV_PCIE_MSI_FLAGS_REQUIRED, > + .supported_flags =3D HV_PCIE_MSI_FLAGS_SUPPORTED, > + .bus_select_token =3D DOMAIN_BUS_PCI_MSI, > + .chip_flags =3D HV_MSI_CHIP_FLAGS, > + .prefix =3D "HV-", > + .init_dev_msi_info =3D hv_pcie_init_dev_msi_info, > +}; > + > /* HW Interrupt Chip Descriptor */ > static struct irq_chip hv_msi_irq_chip =3D { > .name =3D "Hyper-V PCIe MSI", > .irq_compose_msi_msg =3D hv_compose_msi_msg, > .irq_set_affinity =3D irq_chip_set_affinity_parent, > -#ifdef CONFIG_X86 > .irq_ack =3D irq_chip_ack_parent, > - .flags =3D IRQCHIP_MOVE_DEFERRED, > -#elif defined(CONFIG_ARM64) > .irq_eoi =3D irq_chip_eoi_parent, > -#endif > .irq_mask =3D hv_irq_mask, > .irq_unmask =3D hv_irq_unmask, > }; >=20 > -static struct msi_domain_ops hv_msi_ops =3D { > - .msi_prepare =3D hv_msi_prepare, > - .msi_free =3D hv_msi_free, > - .prepare_desc =3D pci_msix_prepare_desc, > +static int hv_pcie_domain_alloc(struct irq_domain *d, unsigned int virq,= unsigned int nr_irqs, > + void *arg) > +{ > + /* > + * TODO: Allocating and populating struct tran_int_desc in hv_compose_m= si_msg() > + * should be moved here. > + */ > + int ret; > + > + ret =3D irq_domain_alloc_irqs_parent(d, virq, nr_irqs, arg); > + if (ret < 0) > + return ret; > + > + for (int i =3D 0; i < nr_irqs; i++) { > + irq_domain_set_hwirq_and_chip(d, virq + i, 0, &hv_msi_irq_chip, NULL); > + if (IS_ENABLED(CONFIG_X86)) > + __irq_set_handler(virq + i, handle_edge_irq, 0, "edge"); > + } > + > + return 0; > +} > + > +static void hv_pcie_domain_free(struct irq_domain *d, unsigned int virq,= unsigned int nr_irqs) > +{ > + struct msi_domain_info *info =3D d->host_data; > + > + for (int i =3D 0; i < nr_irqs; i++) > + hv_msi_free(d, info, virq + i); > + > + irq_domain_free_irqs_top(d, virq, nr_irqs); > +} > + > +static const struct irq_domain_ops hv_pcie_domain_ops =3D { > + .alloc =3D hv_pcie_domain_alloc, > + .free =3D hv_pcie_domain_free, > }; >=20 > /** > @@ -2137,17 +2195,14 @@ static struct msi_domain_ops hv_msi_ops =3D { > */ > static int hv_pcie_init_irq_domain(struct hv_pcibus_device *hbus) > { > - hbus->msi_info.chip =3D &hv_msi_irq_chip; > - hbus->msi_info.ops =3D &hv_msi_ops; > - hbus->msi_info.flags =3D (MSI_FLAG_USE_DEF_DOM_OPS | > - MSI_FLAG_USE_DEF_CHIP_OPS | MSI_FLAG_MULTI_PCI_MSI | > - MSI_FLAG_PCI_MSIX | MSI_FLAG_PCI_MSIX_ALLOC_DYN); > - hbus->msi_info.handler =3D FLOW_HANDLER; > - hbus->msi_info.handler_name =3D FLOW_NAME; > - hbus->msi_info.data =3D hbus; > - hbus->irq_domain =3D pci_msi_create_irq_domain(hbus->fwnode, > - &hbus->msi_info, > - hv_pci_get_root_domain()); > + struct irq_domain_info info =3D { > + .fwnode =3D hbus->fwnode, > + .ops =3D &hv_pcie_domain_ops, > + .host_data =3D hbus, > + .parent =3D hv_pci_get_root_domain(), > + }; > + > + hbus->irq_domain =3D msi_create_parent_irq_domain(&info, &hv_pcie_msi_p= arent_ops); > if (!hbus->irq_domain) { > dev_err(&hbus->hdev->device, > "Failed to build an MSI IRQ domain\n"); > -- > 2.39.5