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Thu, 9 Jul 2026 19:08:47 +0000 Received: from SN6PR02MB4157.namprd02.prod.outlook.com ([fe80::900:1ccf:2b1e:52b6]) by SN6PR02MB4157.namprd02.prod.outlook.com ([fe80::900:1ccf:2b1e:52b6%3]) with mapi id 15.21.0181.014; Thu, 9 Jul 2026 19:08:47 +0000 From: Michael Kelley To: Yu Zhang , "linux-kernel@vger.kernel.org" , "linux-hyperv@vger.kernel.org" , "iommu@lists.linux.dev" , "linux-pci@vger.kernel.org" , "linux-arch@vger.kernel.org" CC: "wei.liu@kernel.org" , "kys@microsoft.com" , "haiyangz@microsoft.com" , "decui@microsoft.com" , "longli@microsoft.com" , "joro@8bytes.org" , "will@kernel.org" , "robin.murphy@arm.com" , "bhelgaas@google.com" , "kwilczynski@kernel.org" , "lpieralisi@kernel.org" , "mani@kernel.org" , "robh@kernel.org" , "arnd@arndb.de" , "jgg@ziepe.ca" , Michael Kelley , "jacob.pan@linux.microsoft.com" , "tgopinath@linux.microsoft.com" , "easwar.hariharan@linux.microsoft.com" , "mrathor@linux.microsoft.com" Subject: RE: [PATCH v2 4/4] iommu/hyperv: Add page-selective IOTLB flush support Thread-Topic: [PATCH v2 4/4] iommu/hyperv: Add page-selective IOTLB flush support Thread-Index: AQHdCjymkcgjkjrpdUyYQ1Fm2oFqarZlmEJw Date: Thu, 9 Jul 2026 19:08:47 +0000 Message-ID: References: <20260702160518.311234-1-zhangyu1@linux.microsoft.com> <20260702160518.311234-5-zhangyu1@linux.microsoft.com> In-Reply-To: <20260702160518.311234-5-zhangyu1@linux.microsoft.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: SN6PR02MB4157:EE_|DM6PR02MB6905:EE_ x-ms-office365-filtering-correlation-id: def0f78a-60b0-4694-1e87-08dedded8119 x-microsoft-antispam: BCL:0;ARA:14566002|13091999003|19110799012|8062599012|8060799015|51005399006|31061999003|19101099003|16051099003|25010399006|37011999003|15080799012|40105399003|12091999003|102099032|3412199025|440099028|1710799026; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN6PR02MB4157.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-CrossTenant-Network-Message-Id: def0f78a-60b0-4694-1e87-08dedded8119 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Jul 2026 19:08:47.5736 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-CrossTenant-rms-persistedconsumerorg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR02MB6905 From: Yu Zhang Sent: Thursday, July 2, 2026 = 9:05 AM >=20 > Add page-selective IOTLB flush using HVCALL_FLUSH_DEVICE_DOMAIN_LIST. > This hypercall accepts a list of (page_number, page_mask_shift) entries, > enabling finer-grained IOTLB invalidation compared to the domain-wide > HVCALL_FLUSH_DEVICE_DOMAIN used by hv_iommu_flush_iotlb_all(). >=20 > hv_iommu_calc_flush_range() computes the smallest power-of-two aligned > range that covers the target IOVA region, producing a single flush > descriptor. This may over-flush when the range is not naturally aligned, > matching the approach used by Intel VT-d PSI. If the page-selective > flush fails, the code falls back to a full domain flush. >=20 > Signed-off-by: Easwar Hariharan > Signed-off-by: Yu Zhang > --- > drivers/iommu/hyperv/iommu.c | 68 +++++++++++++++++++++++++++++++++++- > include/hyperv/hvgdk_mini.h | 1 + > include/hyperv/hvhdk_mini.h | 17 +++++++++ > 3 files changed, 85 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/iommu/hyperv/iommu.c b/drivers/iommu/hyperv/iommu.c > index 254136946404..e9b104a322fd 100644 > --- a/drivers/iommu/hyperv/iommu.c > +++ b/drivers/iommu/hyperv/iommu.c > @@ -9,6 +9,7 @@ > #define pr_fmt(fmt) "Hyper-V pvIOMMU: " fmt > #define dev_fmt(fmt) pr_fmt(fmt) >=20 > +#include > #include > #include > #include > @@ -401,10 +402,74 @@ static void hv_iommu_flush_iotlb_all(struct iommu_d= omain *domain) > hv_flush_device_domain(to_hv_iommu_domain(domain)); > } >=20 > +/* > + * Calculate the minimal power-of-two aligned range that covers [start, = end] > + * (end is inclusive). Returns a single (page_number, page_mask_shift) > + * descriptor that may over-flush when the range is not naturally aligne= d. > + */ > +static void hv_iommu_calc_flush_range(unsigned long start, unsigned long= end, > + union hv_iommu_flush_va *va) > +{ > + unsigned long start_pfn =3D HVPFN_DOWN(start); > + unsigned long last_pfn =3D HVPFN_UP(end + 1) - 1; > + unsigned long mask_shift, aligned_pfn; > + > + if (start_pfn =3D=3D last_pfn) { > + mask_shift =3D 0; > + } else { > + /* > + * Find the highest bit position where start_pfn and last_pfn > + * differ. A range aligned to one above that bit is the > + * smallest power-of-two region that covers both endpoints. > + */ > + mask_shift =3D __fls(start_pfn ^ last_pfn) + 1; > + } > + > + aligned_pfn =3D ALIGN_DOWN(start_pfn, 1UL << mask_shift); > + va->page_number =3D aligned_pfn; > + va->page_mask_shift =3D mask_shift; > +} > + > +static void hv_flush_device_domain_list(struct hv_iommu_domain *hv_domai= n, > + struct iommu_iotlb_gather *iotlb_gather) > +{ > + u64 status; > + unsigned long flags; > + struct hv_input_flush_device_domain_list *input; > + > + local_irq_save(flags); > + > + input =3D *this_cpu_ptr(hyperv_pcpu_input_arg); > + memset(input, 0, sizeof(*input)); > + > + input->device_domain =3D hv_domain->device_domain; > + input->flags |=3D HV_FLUSH_DEVICE_DOMAIN_LIST_IOMMU_FORMAT; > + hv_iommu_calc_flush_range(iotlb_gather->start, iotlb_gather->end, > + &input->iova_list[0]); > + > + status =3D hv_do_rep_hypercall(HVCALL_FLUSH_DEVICE_DOMAIN_LIST, > + 1, 0, input, NULL); > + > + if (!hv_result_success(status)) { > + /* Page-selective flush failed, fall back to full flush. */ With the selective flush now simplified to just a single entry, it really shouldn't fail, right? Doing a full flush as a fallback makes sense, but perhaps do a WARN_ON_ONCE() first so that there's an indication that the selective flush failed. > + struct hv_input_flush_device_domain *flush_all =3D (void *)input; > + > + memset(flush_all, 0, sizeof(*flush_all)); > + flush_all->device_domain =3D hv_domain->device_domain; > + status =3D hv_do_hypercall(HVCALL_FLUSH_DEVICE_DOMAIN, > + flush_all, NULL); > + WARN(!hv_result_success(status), > + "HVCALL_FLUSH_DEVICE_DOMAIN fallback also failed: %lld\n", > + status); > + } > + > + local_irq_restore(flags); > +} > + > static void hv_iommu_iotlb_sync(struct iommu_domain *domain, > struct iommu_iotlb_gather *iotlb_gather) > { > - hv_flush_device_domain(to_hv_iommu_domain(domain)); > + hv_flush_device_domain_list(to_hv_iommu_domain(domain), iotlb_gather); >=20 > iommu_put_pages_list(&iotlb_gather->freelist); > } > @@ -455,6 +520,7 @@ static struct iommu_domain *hv_iommu_domain_alloc_pag= ing(struct device *dev) >=20 > cfg.common.hw_max_vasz_lg2 =3D hv_iommu_device->max_iova_width; > cfg.common.hw_max_oasz_lg2 =3D 52; > + cfg.common.features |=3D BIT(PT_FEAT_FLUSH_RANGE); > cfg.top_level =3D (hv_iommu_device->max_iova_width > 48) ? 4 : 3; >=20 > ret =3D pt_iommu_x86_64_init(&hv_domain->pt_iommu_x86_64, &cfg, GFP_KER= NEL); > diff --git a/include/hyperv/hvgdk_mini.h b/include/hyperv/hvgdk_mini.h > index 5bdbb44da112..eaaf87171478 100644 > --- a/include/hyperv/hvgdk_mini.h > +++ b/include/hyperv/hvgdk_mini.h > @@ -496,6 +496,7 @@ union hv_vp_assist_msr_contents { /* > HV_REGISTER_VP_ASSIST_PAGE */ > #define HVCALL_GET_GPA_PAGES_ACCESS_STATES 0x00c9 > #define HVCALL_CONFIGURE_DEVICE_DOMAIN 0x00ce > #define HVCALL_FLUSH_DEVICE_DOMAIN 0x00d0 > +#define HVCALL_FLUSH_DEVICE_DOMAIN_LIST 0x00d1 > #define HVCALL_ACQUIRE_SPARSE_SPA_PAGE_HOST_ACCESS 0x00d7 > #define HVCALL_RELEASE_SPARSE_SPA_PAGE_HOST_ACCESS 0x00d8 > #define HVCALL_MODIFY_SPARSE_GPA_PAGE_HOST_VISIBILITY 0x00db > diff --git a/include/hyperv/hvhdk_mini.h b/include/hyperv/hvhdk_mini.h > index 493608e791b4..f51d5d9467f1 100644 > --- a/include/hyperv/hvhdk_mini.h > +++ b/include/hyperv/hvhdk_mini.h > @@ -671,4 +671,21 @@ struct hv_input_flush_device_domain { > u32 reserved; > } __packed; >=20 > +union hv_iommu_flush_va { > + u64 iova; > + struct { > + u64 page_mask_shift : 12; > + u64 page_number : 52; > + }; > +} __packed; > + > + > +struct hv_input_flush_device_domain_list { > + struct hv_input_device_domain device_domain; > +#define HV_FLUSH_DEVICE_DOMAIN_LIST_IOMMU_FORMAT (1 << 0) Use BIT()? > + u32 flags; > + u32 reserved; > + union hv_iommu_flush_va iova_list[]; > +} __packed; > + > #endif /* _HV_HVHDK_MINI_H */ > -- > 2.52.0 >=20