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Y . Srinivasan" , Haiyang Zhang , Wei Liu , Dexuan Cui , Joyce Ooi , Jim Quinlan , Nicolas Saenz Julienne , Florian Fainelli , Broadcom internal kernel review list , Ray Jui , Scott Branden , Ryder Lee , Jianjun Wang , Marek Vasut , Yoshihiro Shimoda , Michal Simek , Daire McNamara , Nirmal Patel , Jonathan Derrick , Matthias Brugger , AngeloGioacchino Del Regno , "linux-arm-kernel@lists.infradead.org" , "linux-hyperv@vger.kernel.org" , "linux-rpi-kernel@lists.infradead.org" , "linux-mediatek@lists.infradead.org" , "linux-renesas-soc@vger.kernel.org" Subject: RE: [PATCH 14/16] PCI: hv: Switch to msi_create_parent_irq_domain() Thread-Topic: [PATCH 14/16] PCI: hv: Switch to msi_create_parent_irq_domain() Thread-Index: AQHb5qqGWI9T0Ene10yNxUr1s0p/CbQgsvtA Date: Thu, 3 Jul 2025 17:41:19 +0000 Message-ID: References: <024f0122314198fe0a42fef01af53e8953a687ec.1750858083.git.namcao@linutronix.de> In-Reply-To: <024f0122314198fe0a42fef01af53e8953a687ec.1750858083.git.namcao@linutronix.de> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: SN6PR02MB4157:EE_|SN7PR02MB10177:EE_ x-ms-office365-filtering-correlation-id: 1a7b9f80-e47d-4e33-f013-08ddba58d183 x-microsoft-antispam: BCL:0;ARA:14566002|8062599006|461199028|41001999006|19110799006|15080799009|31055399003|440099028|53005399003|3412199025|40105399003|19111999003|12091999003|102099032; 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charset="iso-8859-2" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: SN6PR02MB4157.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-CrossTenant-Network-Message-Id: 1a7b9f80-e47d-4e33-f013-08ddba58d183 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Jul 2025 17:41:19.1261 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-CrossTenant-rms-persistedconsumerorg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR02MB10177 From: Nam Cao Sent: Thursday, June 26, 2025 7:48 AM >=20 > Move away from the legacy MSI domain setup, switch to use > msi_create_parent_irq_domain(). >From a build standpoint, this patch does not apply cleanly to linux-next20250630. See also an issue below where a needed irq function isn't exported. At runtime, I've done basic smoke testing on an x86 VM in the Azure cloud that has a Mellanox NIC VF and two NVMe devices as PCI devices. So far everything looks good. But I'm still doing additional testing, and I want to also test on an ARM64 VM. Please give me another day or two to be completely satisfied. Michael Kelley >=20 > Signed-off-by: Nam Cao > --- > Cc: K. Y. Srinivasan > Cc: Haiyang Zhang > Cc: Wei Liu > Cc: Dexuan Cui > Cc: linux-hyperv@vger.kernel.org > --- > drivers/pci/Kconfig | 1 + > drivers/pci/controller/pci-hyperv.c | 98 +++++++++++++++++++++++------ > 2 files changed, 80 insertions(+), 19 deletions(-) >=20 > diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig > index 9c0e4aaf4e8cb..9a249c65aedcd 100644 > --- a/drivers/pci/Kconfig > +++ b/drivers/pci/Kconfig > @@ -223,6 +223,7 @@ config PCI_HYPERV > tristate "Hyper-V PCI Frontend" > depends on ((X86 && X86_64) || ARM64) && HYPERV && PCI_MSI && SYSFS > select PCI_HYPERV_INTERFACE > + select IRQ_MSI_LIB > help > The PCI device frontend driver allows the kernel to import arbitrary > PCI devices from a PCI backend to support PCI driver domains. > diff --git a/drivers/pci/controller/pci-hyperv.c b/drivers/pci/controller= /pci-hyperv.c > index ef5d655a0052c..3a24fadddb83b 100644 > --- a/drivers/pci/controller/pci-hyperv.c > +++ b/drivers/pci/controller/pci-hyperv.c > @@ -44,6 +44,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -508,7 +509,6 @@ struct hv_pcibus_device { > struct list_head children; > struct list_head dr_list; >=20 > - struct msi_domain_info msi_info; > struct irq_domain *irq_domain; >=20 > struct workqueue_struct *wq; > @@ -1687,7 +1687,7 @@ static void hv_msi_free(struct irq_domain *domain, = struct msi_domain_info *info, > struct msi_desc *msi =3D irq_data_get_msi_desc(irq_data); >=20 > pdev =3D msi_desc_to_pci_dev(msi); > - hbus =3D info->data; > + hbus =3D domain->host_data; > int_desc =3D irq_data_get_irq_chip_data(irq_data); > if (!int_desc) > return; > @@ -1705,7 +1705,6 @@ static void hv_msi_free(struct irq_domain *domain, = struct msi_domain_info *info, >=20 > static void hv_irq_mask(struct irq_data *data) > { > - pci_msi_mask_irq(data); > if (data->parent_data->chip->irq_mask) > irq_chip_mask_parent(data); > } > @@ -1716,7 +1715,6 @@ static void hv_irq_unmask(struct irq_data *data) >=20 > if (data->parent_data->chip->irq_unmask) > irq_chip_unmask_parent(data); > - pci_msi_unmask_irq(data); > } >=20 > struct compose_comp_ctxt { > @@ -2101,6 +2099,44 @@ static void hv_compose_msi_msg(struct irq_data *da= ta, struct msi_msg *msg) > msg->data =3D 0; > } >=20 > +static bool hv_pcie_init_dev_msi_info(struct device *dev, struct irq_dom= ain *domain, > + struct irq_domain *real_parent, struct msi_domain_info *info) > +{ > + struct irq_chip *chip =3D info->chip; > + > + if (!msi_lib_init_dev_msi_info(dev, domain, real_parent, info)) > + return false; > + > + info->ops->msi_prepare =3D hv_msi_prepare; > + > + chip->irq_set_affinity =3D irq_chip_set_affinity_parent; > + > + if (IS_ENABLED(CONFIG_X86)) > + chip->flags |=3D IRQCHIP_MOVE_DEFERRED; > + > + return true; > +} > + > +#define HV_PCIE_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS > | \ > + MSI_FLAG_USE_DEF_CHIP_OPS | \ > + MSI_FLAG_PCI_MSI_MASK_PARENT) > +#define HV_PCIE_MSI_FLAGS_SUPPORTED (MSI_FLAG_MULTI_PCI_MSI > | \ > + MSI_FLAG_PCI_MSIX | \ > + MSI_GENERIC_FLAGS_MASK) > + > +static const struct msi_parent_ops hv_pcie_msi_parent_ops =3D { > + .required_flags =3D HV_PCIE_MSI_FLAGS_REQUIRED, > + .supported_flags =3D HV_PCIE_MSI_FLAGS_SUPPORTED, > + .bus_select_token =3D DOMAIN_BUS_PCI_MSI, > +#ifdef CONFIG_X86 > + .chip_flags =3D MSI_CHIP_FLAG_SET_ACK, > +#elif defined(CONFIG_ARM64) > + .chip_flags =3D MSI_CHIP_FLAG_SET_EOI, > +#endif > + .prefix =3D "HV-", > + .init_dev_msi_info =3D hv_pcie_init_dev_msi_info, > +}; > + > /* HW Interrupt Chip Descriptor */ > static struct irq_chip hv_msi_irq_chip =3D { > .name =3D "Hyper-V PCIe MSI", > @@ -2108,7 +2144,6 @@ static struct irq_chip hv_msi_irq_chip =3D { > .irq_set_affinity =3D irq_chip_set_affinity_parent, > #ifdef CONFIG_X86 > .irq_ack =3D irq_chip_ack_parent, > - .flags =3D IRQCHIP_MOVE_DEFERRED, > #elif defined(CONFIG_ARM64) > .irq_eoi =3D irq_chip_eoi_parent, > #endif > @@ -2116,9 +2151,37 @@ static struct irq_chip hv_msi_irq_chip =3D { > .irq_unmask =3D hv_irq_unmask, > }; >=20 > -static struct msi_domain_ops hv_msi_ops =3D { > - .msi_prepare =3D hv_msi_prepare, > - .msi_free =3D hv_msi_free, > +static int hv_pcie_domain_alloc(struct irq_domain *d, unsigned int virq,= unsigned int nr_irqs, > + void *arg) > +{ > + /* TODO: move the content of hv_compose_msi_msg() in here */ > + int ret; > + > + ret =3D irq_domain_alloc_irqs_parent(d, virq, nr_irqs, arg); > + if (ret < 0) > + return ret; > + > + for (int i =3D 0; i < nr_irqs; i++) { > + irq_domain_set_info(d, virq + i, 0, &hv_msi_irq_chip, NULL, FLOW_HANDL= ER, NULL, > + FLOW_NAME); > + } > + > + return 0; > +} > + > +static void hv_pcie_domain_free(struct irq_domain *d, unsigned int virq,= unsigned int nr_irqs) > +{ > + struct msi_domain_info *info =3D d->host_data; > + > + for (int i =3D 0; i < nr_irqs; i++) > + hv_msi_free(d, info, virq + i); > + > + irq_domain_free_irqs_top(d, virq, nr_irqs); This code can be built as a module, so irq_domain_free_irqs_top() needs to = be exported, which it currently is not. > +} > + > +static const struct irq_domain_ops hv_pcie_domain_ops =3D { > + .alloc =3D hv_pcie_domain_alloc, > + .free =3D hv_pcie_domain_free, > }; >=20 > /** > @@ -2136,17 +2199,14 @@ static struct msi_domain_ops hv_msi_ops =3D { > */ > static int hv_pcie_init_irq_domain(struct hv_pcibus_device *hbus) > { > - hbus->msi_info.chip =3D &hv_msi_irq_chip; > - hbus->msi_info.ops =3D &hv_msi_ops; > - hbus->msi_info.flags =3D (MSI_FLAG_USE_DEF_DOM_OPS | > - MSI_FLAG_USE_DEF_CHIP_OPS | MSI_FLAG_MULTI_PCI_MSI | > - MSI_FLAG_PCI_MSIX); > - hbus->msi_info.handler =3D FLOW_HANDLER; > - hbus->msi_info.handler_name =3D FLOW_NAME; > - hbus->msi_info.data =3D hbus; > - hbus->irq_domain =3D pci_msi_create_irq_domain(hbus->fwnode, > - &hbus->msi_info, > - hv_pci_get_root_domain()); > + struct irq_domain_info info =3D { > + .fwnode =3D hbus->fwnode, > + .ops =3D &hv_pcie_domain_ops, > + .host_data =3D hbus, > + .parent =3D hv_pci_get_root_domain(), > + }; > + > + hbus->irq_domain =3D msi_create_parent_irq_domain(&info, &hv_pcie_msi_p= arent_ops); > if (!hbus->irq_domain) { > dev_err(&hbus->hdev->device, > "Failed to build an MSI IRQ domain\n"); > -- > 2.39.5 >=20