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IPQ5332 UNIPHY USB Super-speed PHY To: Konrad Dybcio , Krzysztof Kozlowski Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Praveenkumar I , Varadarajan Narayanan , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Greg Kroah-Hartman , Wesley Cheng , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-usb@vger.kernel.org References: <20260812-ipq5018-usb3-v2-0-8f355d7ff0ef@outlook.com> <20260812-ipq5018-usb3-v2-1-8f355d7ff0ef@outlook.com> <20260813-alluring-advanced-jackalope-55e5c1@quoll> <71cfe76b-ea84-47f8-9ff7-945d69efbdcd@kernel.org> <34503ae2-9c89-4773-af80-fa7b7439ff23@oss.qualcomm.com> Content-Language: en-US From: George Moussalem In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-ClientProxiedBy: DX0P273CA0009.AREP273.PROD.OUTLOOK.COM (2603:1086:300:26::17) To SN7PR19MB6736.namprd19.prod.outlook.com (2603:10b6:806:263::12) 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X-MS-Exchange-CrossTenant-AuthSource: SN7PR19MB6736.namprd19.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Aug 2026 12:45:38.2020 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR19MB6049 On 8/17/26 16:38, Konrad Dybcio wrote: > On 8/17/26 2:37 PM, Konrad Dybcio wrote: >> On 8/13/26 12:48 PM, Krzysztof Kozlowski wrote: >>> On 13/08/2026 12:28, George Moussalem wrote: >>>>>> +examples: >>>>>> + - | >>>>>> + #include >>>>>> + >>>>>> + phy@4b0000 { >>>>>> + compatible = "qcom,ipq5332-uniphy-usb-ss-phy"; >>>>>> + reg = <0x4b0000 0x800>; >>>>> >>>>> That is the same address as PCI PHY, so you have one device, not two. >>>> >>>> yes, AFAIK they're separate PHYs (pcie-28lp vs usb-ss-22ull) sharing the >>>> same MMIO register space in IPQ5332. To enable USB3, the compatible >>>> string, clocks, resets, and related USB3 properties override the PCIe >>>> properties. In IPQ5018, the PHYs have different register address spaces, >>>> hence representing it as a new devicetree node. >>>> >>> >>> Same MMIO space is same device, IMO, especially that you have the same >>> registers (looking at the driver). >> >> It's indeed one device, fittingly named "PCIE+USB COMBO PHY" > > so the implementation, matching prior art for similar cases should be: > > - phy node with #phy-cells = <1> > - consumer takes a reference through phys = <&phy FOO_PCIE> or FOO_USB3 > - new driver in drivers/phy/qualcomm to coordinate the two modes Thanks for confirming it's one device. I'm already working on a new version using phy-cells and having the consumer select the phy type. However: I'm adjusting the existing phy-qcom-uniphy-pcie-28lp.c as that's the driver currently used for PCIe only in both IPQ5018 and IPQ5332. So I'm adjusting it to register 2 PHYs and provide both PCIe and USB functionality. Any objections/concerns? > > Konrad Best regards, George