Re: [PATCH] x86/tsc: Read AMD CPU frequency from Core::X86::Msr::PStateDef

[Stephen Horvath <s.horvath@outlook.com.au>]

Hi Borislav, Thank you very much for reviewing my patch!

On 15/8/25 01:25, Borislav Petkov wrote:
> On Wed, Aug 13, 2025 at 11:23:38AM +0000, Stephen Horvath wrote:
>> +	/* The PPR defines the core multiplier as CpuFid * 25MHz */
>> +	p0_freq = cpufid * 25;
> 
> As someone already pointed out:

Was this pointed out publicly, or something internally? I couldn't find
any relevant TSC patches for AMD on lore when I looked previously (other
than the Secure TSC which didn't seem applicable).

> 
> PPR Vol 1 for AMD Family 1Ah Model 02h C1
> 
> ...
> 
> MSRC001_006[4...B] [P-state [7:0]] (Core::X86::Msr::PStateDef)
> 
> ...
> 
> CpuFid[11:0]: core frequency ID.
> 
> FFFh- <Value>*5
> 010h
> 
> So we need to do per-family checks here.

Ah, good catch! I did check through the 17h and 19h PPRs, but overlooked
1Ah. At least 1Ah is simpler since there's no divisor.

> 
> Not sure if that is worth it, frankly.
> 

Yeah that's fair enough. I might submit a v2 with some changes next week
and leave it at that, depending on feedback from others.

Thank you again for your time reviewing this!
Steve.