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charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: fujitsu.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TY2PR01MB5257.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: b9bc2f7b-81fc-4f0a-7db6-08d9c36ec42f X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Dec 2021 04:11:15.4432 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a19f121d-81e1-4858-a9d8-736e267fd4c7 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: mod9T2Gv2Eoqxc8vOtn7Y2nSOB3/6qTOTSl5dBCJwkyYSdojIPWscfkWkEpULWQ7f3B7rMlnBIshJW+3/GPLOBsbWaJvSOJuagaQlZdmVVc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYAPR01MB2991 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, =0A= =0A= > > Avoid this fault by calling aarch64_insn_write() to update the instruct= ion=0A= > > if the module text has already been marked read-only. Preserve the curr= ent=0A= > > behaviour if called before this has been done.=0A= > >=0A= > > Signed-off-by: Suraj Jitindar Singh =0A= > > ---=0A= > > arch/arm64/kernel/module.c | 81 ++++++++++++++++++++++----------------= =0A= > > 1 file changed, 47 insertions(+), 34 deletions(-)=0A= > >=0A= > > diff --git a/arch/arm64/kernel/module.c b/arch/arm64/kernel/module.c=0A= > > index b5ec010c481f..35596ea870ab 100644=0A= > > --- a/arch/arm64/kernel/module.c=0A= > > +++ b/arch/arm64/kernel/module.c=0A= > > @@ -19,6 +19,7 @@=0A= > > #include =0A= > > #include =0A= > > #include =0A= > > +#include =0A= > >=0A= > > void *module_alloc(unsigned long size)=0A= > > {=0A= > > @@ -155,7 +156,8 @@ enum aarch64_insn_movw_imm_type {=0A= > > };=0A= > >=0A= > > static int reloc_insn_movw(enum aarch64_reloc_op op, __le32 *place, u6= 4 val,=0A= > > - int lsb, enum aarch64_insn_movw_imm_type imm_type)=0A= > > + int lsb, enum aarch64_insn_movw_imm_type imm_type,=0A= > > + bool early)=0A= > > {=0A= > > u64 imm;=0A= > > s64 sval;=0A= > > @@ -187,7 +189,10 @@ static int reloc_insn_movw(enum aarch64_reloc_op o= p, __le32 *place, u64 val,=0A= > >=0A= > > /* Update the instruction with the new encoding. */=0A= > > insn =3D aarch64_insn_encode_immediate(AARCH64_INSN_IMM_16, insn, imm= );=0A= > > - *place =3D cpu_to_le32(insn);=0A= > > + if (early)=0A= > > + *place =3D cpu_to_le32(insn);=0A= > > + else=0A= > > + aarch64_insn_write(place, insn);=0A= > =0A= > If we really need this, I think it'd be better to refactor the=0A= > reloc_insn_*() helpers to generate the new encoding into a temporary=0A= > buffer, and make it the caller's responsibiltiy to then perform the=0A= > write to the real location in the module.=0A= > =0A= > That way we only have to handle the "early" distinction in one place=0A= > rather than spreading it out.=0A= > =0A= > I see you haven't altered the reloc_data() function -- does livepatch=0A= > never result in data relocations?=0A= > =0A= > Thanks,=0A= > Mark.=0A= > =0A= =0A= Livepatch can also result in data relocation.=0A= =0A= So I wrote data relocation test with kpatch and send pull-request [1].=0A= Suraj, please try it if you would like.=0A= =0A= [1] https://github.com/dynup/kpatch/pull/1244=0A= =0A= Thanks,=0A= Keiya=0A= =0A= > >=0A= > > if (imm > U16_MAX)=0A= > > return -ERANGE;=0A= > > @@ -196,7 +201,8 @@ static int reloc_insn_movw(enum aarch64_reloc_op op= , __le32 *place, u64 val,=0A= > > }=0A= > >=0A= > > static int reloc_insn_imm(enum aarch64_reloc_op op, __le32 *place, u64= val,=0A= > > - int lsb, int len, enum aarch64_insn_imm_type imm_type)=0A= > > + int lsb, int len, enum aarch64_insn_imm_type imm_type,=0A= > > + bool early)=0A= > > {=0A= > > u64 imm, imm_mask;=0A= > > s64 sval;=0A= > > @@ -212,7 +218,10 @@ static int reloc_insn_imm(enum aarch64_reloc_op op= , __le32 *place, u64 val,=0A= > >=0A= > > /* Update the instruction's immediate field. */=0A= > > insn =3D aarch64_insn_encode_immediate(imm_type, insn, imm);=0A= > > - *place =3D cpu_to_le32(insn);=0A= > > + if (early)=0A= > > + *place =3D cpu_to_le32(insn);=0A= > > + else=0A= > > + aarch64_insn_write(place, insn);=0A= > >=0A= > > /*=0A= > > * Extract the upper value bits (including the sign bit) and=0A= > > @@ -231,17 +240,17 @@ static int reloc_insn_imm(enum aarch64_reloc_op o= p, __le32 *place, u64 val,=0A= > > }=0A= > >=0A= > > static int reloc_insn_adrp(struct module *mod, Elf64_Shdr *sechdrs,=0A= > > - __le32 *place, u64 val)=0A= > > + __le32 *place, u64 val, bool early)=0A= > > {=0A= > > u32 insn;=0A= > >=0A= > > if (!is_forbidden_offset_for_adrp(place))=0A= > > return reloc_insn_imm(RELOC_OP_PAGE, place, val, 12, 21,=0A= > > - AARCH64_INSN_IMM_ADR);=0A= > > + AARCH64_INSN_IMM_ADR, early);=0A= > >=0A= > > /* patch ADRP to ADR if it is in range */=0A= > > if (!reloc_insn_imm(RELOC_OP_PREL, place, val & ~0xfff, 0, 21,=0A= > > - AARCH64_INSN_IMM_ADR)) {=0A= > > + AARCH64_INSN_IMM_ADR, early)) {=0A= > > insn =3D le32_to_cpu(*place);=0A= > > insn &=3D ~BIT(31);=0A= > > } else {=0A= > > @@ -253,7 +262,10 @@ static int reloc_insn_adrp(struct module *mod, Elf= 64_Shdr *sechdrs,=0A= > > AARCH64_INSN_BRANCH_NOLINK);=0A= > > }=0A= > >=0A= > > - *place =3D cpu_to_le32(insn);=0A= > > + if (early)=0A= > > + *place =3D cpu_to_le32(insn);=0A= > > + else=0A= > > + aarch64_insn_write(place, insn);=0A= > > return 0;=0A= > > }=0A= > >=0A= > > @@ -270,6 +282,7 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,=0A= > > void *loc;=0A= > > u64 val;=0A= > > Elf64_Rela *rel =3D (void *)sechdrs[relsec].sh_addr;=0A= > > + bool early =3D me->state =3D=3D MODULE_STATE_UNFORMED;=0A= > >=0A= > > for (i =3D 0; i < sechdrs[relsec].sh_size / sizeof(*rel); i++) {=0A= > > /* loc corresponds to P in the AArch64 ELF document. */=0A= > > @@ -322,88 +335,88 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,=0A= > > fallthrough;=0A= > > case R_AARCH64_MOVW_UABS_G0:=0A= > > ovf =3D reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,=0A= > > - AARCH64_INSN_IMM_MOVKZ);=0A= > > + AARCH64_INSN_IMM_MOVKZ, early);=0A= > > break;=0A= > > case R_AARCH64_MOVW_UABS_G1_NC:=0A= > > overflow_check =3D false;=0A= > > fallthrough;=0A= > > case R_AARCH64_MOVW_UABS_G1:=0A= > > ovf =3D reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,=0A= > > - AARCH64_INSN_IMM_MOVKZ);=0A= > > + AARCH64_INSN_IMM_MOVKZ, early);=0A= > > break;=0A= > > case R_AARCH64_MOVW_UABS_G2_NC:=0A= > > overflow_check =3D false;=0A= > > fallthrough;=0A= > > case R_AARCH64_MOVW_UABS_G2:=0A= > > ovf =3D reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,=0A= > > - AARCH64_INSN_IMM_MOVKZ);=0A= > > + AARCH64_INSN_IMM_MOVKZ, early);=0A= > > break;=0A= > > case R_AARCH64_MOVW_UABS_G3:=0A= > > /* We're using the top bits so we can't overflow. */=0A= > > overflow_check =3D false;=0A= > > ovf =3D reloc_insn_movw(RELOC_OP_ABS, loc, val, 48,=0A= > > - AARCH64_INSN_IMM_MOVKZ);=0A= > > + AARCH64_INSN_IMM_MOVKZ, early);=0A= > > break;=0A= > > case R_AARCH64_MOVW_SABS_G0:=0A= > > ovf =3D reloc_insn_movw(RELOC_OP_ABS, loc, val, 0,=0A= > > - AARCH64_INSN_IMM_MOVNZ);=0A= > > + AARCH64_INSN_IMM_MOVNZ, early);=0A= > > break;=0A= > > case R_AARCH64_MOVW_SABS_G1:=0A= > > ovf =3D reloc_insn_movw(RELOC_OP_ABS, loc, val, 16,=0A= > > - AARCH64_INSN_IMM_MOVNZ);=0A= > > + AARCH64_INSN_IMM_MOVNZ, early);=0A= > > break;=0A= > > case R_AARCH64_MOVW_SABS_G2:=0A= > > ovf =3D reloc_insn_movw(RELOC_OP_ABS, loc, val, 32,=0A= > > - AARCH64_INSN_IMM_MOVNZ);=0A= > > + AARCH64_INSN_IMM_MOVNZ, early);=0A= > > break;=0A= > > case R_AARCH64_MOVW_PREL_G0_NC:=0A= > > overflow_check =3D false;=0A= > > ovf =3D reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,=0A= > > - AARCH64_INSN_IMM_MOVKZ);=0A= > > + AARCH64_INSN_IMM_MOVKZ, early);=0A= > > break;=0A= > > case R_AARCH64_MOVW_PREL_G0:=0A= > > ovf =3D reloc_insn_movw(RELOC_OP_PREL, loc, val, 0,=0A= > > - AARCH64_INSN_IMM_MOVNZ);=0A= > > + AARCH64_INSN_IMM_MOVNZ, early);=0A= > > break;=0A= > > case R_AARCH64_MOVW_PREL_G1_NC:=0A= > > overflow_check =3D false;=0A= > > ovf =3D reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,=0A= > > - AARCH64_INSN_IMM_MOVKZ);=0A= > > + AARCH64_INSN_IMM_MOVKZ, early);=0A= > > break;=0A= > > case R_AARCH64_MOVW_PREL_G1:=0A= > > ovf =3D reloc_insn_movw(RELOC_OP_PREL, loc, val, 16,=0A= > > - AARCH64_INSN_IMM_MOVNZ);=0A= > > + AARCH64_INSN_IMM_MOVNZ, early);=0A= > > break;=0A= > > case R_AARCH64_MOVW_PREL_G2_NC:=0A= > > overflow_check =3D false;=0A= > > ovf =3D reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,=0A= > > - AARCH64_INSN_IMM_MOVKZ);=0A= > > + AARCH64_INSN_IMM_MOVKZ, early);=0A= > > break;=0A= > > case R_AARCH64_MOVW_PREL_G2:=0A= > > ovf =3D reloc_insn_movw(RELOC_OP_PREL, loc, val, 32,=0A= > > - AARCH64_INSN_IMM_MOVNZ);=0A= > > + AARCH64_INSN_IMM_MOVNZ, early);=0A= > > break;=0A= > > case R_AARCH64_MOVW_PREL_G3:=0A= > > /* We're using the top bits so we can't overflow. */=0A= > > overflow_check =3D false;=0A= > > ovf =3D reloc_insn_movw(RELOC_OP_PREL, loc, val, 48,=0A= > > - AARCH64_INSN_IMM_MOVNZ);=0A= > > + AARCH64_INSN_IMM_MOVNZ, early);=0A= > > break;=0A= > >=0A= > > /* Immediate instruction relocations. */=0A= > > case R_AARCH64_LD_PREL_LO19:=0A= > > ovf =3D reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,=0A= > > - AARCH64_INSN_IMM_19);=0A= > > + AARCH64_INSN_IMM_19, early);=0A= > > break;=0A= > > case R_AARCH64_ADR_PREL_LO21:=0A= > > ovf =3D reloc_insn_imm(RELOC_OP_PREL, loc, val, 0, 21,=0A= > > - AARCH64_INSN_IMM_ADR);=0A= > > + AARCH64_INSN_IMM_ADR, early);=0A= > > break;=0A= > > case R_AARCH64_ADR_PREL_PG_HI21_NC:=0A= > > overflow_check =3D false;=0A= > > fallthrough;=0A= > > case R_AARCH64_ADR_PREL_PG_HI21:=0A= > > - ovf =3D reloc_insn_adrp(me, sechdrs, loc, val);=0A= > > + ovf =3D reloc_insn_adrp(me, sechdrs, loc, val, early);=0A= > > if (ovf && ovf !=3D -ERANGE)=0A= > > return ovf;=0A= > > break;=0A= > > @@ -411,40 +424,40 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,=0A= > > case R_AARCH64_LDST8_ABS_LO12_NC:=0A= > > overflow_check =3D false;=0A= > > ovf =3D reloc_insn_imm(RELOC_OP_ABS, loc, val, 0, 12,=0A= > > - AARCH64_INSN_IMM_12);=0A= > > + AARCH64_INSN_IMM_12, early);=0A= > > break;=0A= > > case R_AARCH64_LDST16_ABS_LO12_NC:=0A= > > overflow_check =3D false;=0A= > > ovf =3D reloc_insn_imm(RELOC_OP_ABS, loc, val, 1, 11,=0A= > > - AARCH64_INSN_IMM_12);=0A= > > + AARCH64_INSN_IMM_12, early);=0A= > > break;=0A= > > case R_AARCH64_LDST32_ABS_LO12_NC:=0A= > > overflow_check =3D false;=0A= > > ovf =3D reloc_insn_imm(RELOC_OP_ABS, loc, val, 2, 10,=0A= > > - AARCH64_INSN_IMM_12);=0A= > > + AARCH64_INSN_IMM_12, early);=0A= > > break;=0A= > > case R_AARCH64_LDST64_ABS_LO12_NC:=0A= > > overflow_check =3D false;=0A= > > ovf =3D reloc_insn_imm(RELOC_OP_ABS, loc, val, 3, 9,=0A= > > - AARCH64_INSN_IMM_12);=0A= > > + AARCH64_INSN_IMM_12, early);=0A= > > break;=0A= > > case R_AARCH64_LDST128_ABS_LO12_NC:=0A= > > overflow_check =3D false;=0A= > > ovf =3D reloc_insn_imm(RELOC_OP_ABS, loc, val, 4, 8,=0A= > > - AARCH64_INSN_IMM_12);=0A= > > + AARCH64_INSN_IMM_12, early);=0A= > > break;=0A= > > case R_AARCH64_TSTBR14:=0A= > > ovf =3D reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 14,=0A= > > - AARCH64_INSN_IMM_14);=0A= > > + AARCH64_INSN_IMM_14, early);=0A= > > break;=0A= > > case R_AARCH64_CONDBR19:=0A= > > ovf =3D reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 19,=0A= > > - AARCH64_INSN_IMM_19);=0A= > > + AARCH64_INSN_IMM_19, early);=0A= > > break;=0A= > > case R_AARCH64_JUMP26:=0A= > > case R_AARCH64_CALL26:=0A= > > ovf =3D reloc_insn_imm(RELOC_OP_PREL, loc, val, 2, 26,=0A= > > - AARCH64_INSN_IMM_26);=0A= > > + AARCH64_INSN_IMM_26, early);=0A= > >=0A= > > if (IS_ENABLED(CONFIG_ARM64_MODULE_PLTS) &&=0A= > > ovf =3D=3D -ERANGE) {=0A= > > @@ -452,7 +465,7 @@ int apply_relocate_add(Elf64_Shdr *sechdrs,=0A= > > if (!val)=0A= > > return -ENOEXEC;=0A= > > ovf =3D reloc_insn_imm(RELOC_OP_PREL, loc, val, 2,=0A= > > - 26, AARCH64_INSN_IMM_26);=0A= > > + 26, AARCH64_INSN_IMM_26, early);=0A= > > }=0A= > > break;=0A= > >=0A= > > --=0A= > > 2.17.1=0A= > >=0A=