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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: bp.renesas.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TY3PR01MB11346.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: a25910dd-dd48-453f-c6bc-08dedbfe5659 X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Jul 2026 08:04:14.9532 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: OyhVRa4qSrN7wiySi0bJ6jZxM1Ppr/SRqj/zPuLN17jJU086h+cgYPNGdnlWHcmVPhNSX5g3+MznhC8R5cWdNxzjRQKB21Q0mpQq/lha84s= X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYRPR01MB13340 Hi Wolfram, > -----Original Message----- > From: Biju Das > Sent: 17 June 2026 13:43 > Subject: RE: [PATCH v17 01/17] dt-bindings: mmc: renesas,sdhi: Document R= Z/G3L (r9a08g046) SoC >=20 > Hi Wolfram, >=20 > Thanks for the feedback. >=20 > > -----Original Message----- > > From: Wolfram Sang > > Sent: 17 June 2026 13:20 > > Subject: Re: [PATCH v17 01/17] dt-bindings: mmc: renesas,sdhi: > > Document RZ/G3L (r9a08g046) SoC > > > > Hi Biju, > > > > On Wed, Jun 03, 2026 at 07:57:01AM +0100, Biju wrote: > > > From: Biju Das > > > > > > Document the RZ/G3L (r9a08g046) SDHI controller. The RZ/G3L SDHI > > > controller is similar to RZ/G2L but has five clocks (core, clkh, cd, > > > aclk, aclkm) and three resets (rst, axim, axis), so update the > > > clocks/clock-names maximum to 5 and resets/reset-names maximum to 3. > > > It has an internal divider for all modes except HS400, and a > > > 2048-bit divider compared to 512 on others. > > > > > > Acked-by: Conor Dooley > > > Signed-off-by: Biju Das > > > > I know you work on v18 already, but some high level remarks already. >=20 > OK. >=20 > > > > > + - description: ACLK/IACLKS, SDHI channel bus clock. > > > + - description: IACLKM, SDHI channel bus clock m. > > > > What does 's' and 'm' stand for? Is it mentioned in the docs? Would be = nice to have here as well, if > so. >=20 > > > > > + resets: > > > + items: > > > + - description: rst, Core reset. > > > + - description: axim, SDHI axi bus reset m. > > > + - description: axis, SDHI axi bus reset s. > > > > Ditto. >=20 > The reset signal mentioned in the hardware manual are SDHIx_IXRST, SDHIx_= IXRSTAXIM and SDHIx_IXRSTAXIS > (where x=3D0,1,2) >=20 > I will check this as well with hardware/documentation team and update you= . I got feedback from hardware team These clocks and reset signals are intended for the AXI Master and AXI Slav= e interfaces. Do you agree free the below description? please let me know. - description: ACLK/IACLKM, SDHI channel bus clock/ AXI maste= r bus clock. - description: IACLKS, SDHI channel AXI slave bus clock. clock-names: items: - const: core - const: clkh - const: cd - const: aclkm - const: aclks resets: items: - description: rst, Core reset. - description: axim, SDHI AXI master bus reset. - description: axis, SDHI AXI slave bus reset. Cheers, Biju