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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: bp.renesas.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TY3PR01MB11346.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 14f2db7c-8d92-479e-a04f-08de9f0598c4 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Apr 2026 17:52:31.9554 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: hpvrvqX2lcavZ35tCra2hhvrVOrui3AeCPe57UDMogc5EDY1kb5LvDXgTfudtimoAurFhUpFBbnw70riw0Acjia6ZGgvQbEeG/bBIpVaUXM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: OS9PR01MB17044 Hi, > -----Original Message----- > From: Biju > Sent: 20 April 2026 11:43 > Subject: [PATCH v5 6/9] pwm: rzg2l-gpt: Add prescale_mult variable to str= uct rzg2l_gpt_info >=20 > From: Biju Das >=20 > RZ/G3E GPT IP has prescale factor power of 2 where as that of RZ/G2L is 4= . > Add prescale_mult variable to struct rzg2l_gpt_info for handling this dif= ference. >=20 > Reviewed-by: Tommaso Merciai > Signed-off-by: Biju Das > --- > v4->v5: > * No change. > v3->v4: > * Updated commit header and description > * Renamed prescale_pow_of_two_mult_factor->prescale_mult > v2->v3: > * No change. > v1->v2: > * Collected tag. > --- > drivers/pwm/pwm-rzg2l-gpt.c | 19 +++++++++++++------ > 1 file changed, 13 insertions(+), 6 deletions(-) >=20 > diff --git a/drivers/pwm/pwm-rzg2l-gpt.c b/drivers/pwm/pwm-rzg2l-gpt.c in= dex af594c1ce536..4324ffc8629d > 100644 > --- a/drivers/pwm/pwm-rzg2l-gpt.c > +++ b/drivers/pwm/pwm-rzg2l-gpt.c > @@ -92,6 +92,7 @@ >=20 > struct rzg2l_gpt_info { > u32 gtcr_tpcs; > + u8 prescale_mult; > }; >=20 > struct rzg2l_gpt_chip { > @@ -234,6 +235,7 @@ static void rzg2l_gpt_disable(struct rzg2l_gpt_chip *= rzg2l_gpt, static u64 > rzg2l_gpt_calculate_period_or_duty(struct rzg2l_gpt_chip *rzg2l_gpt, > u32 val, u8 prescale) > { > + const struct rzg2l_gpt_info *info =3D rzg2l_gpt->info; > u64 tmp; >=20 > /* > @@ -243,15 +245,18 @@ static u64 rzg2l_gpt_calculate_period_or_duty(struc= t rzg2l_gpt_chip *rzg2l_gpt, > * < 2^32 * 2^10 * 2^20 > * =3D 2^62 > */ > - tmp =3D (u64)val << (2 * prescale); > + tmp =3D (u64)val << (info->prescale_mult * prescale); > tmp *=3D USEC_PER_SEC; >=20 > return DIV64_U64_ROUND_UP(tmp, rzg2l_gpt->rate_khz); } >=20 > -static u32 rzg2l_gpt_calculate_pv_or_dc(u64 period_or_duty_cycle, u8 pre= scale) > +static u32 rzg2l_gpt_calculate_pv_or_dc(const struct rzg2l_gpt_info *inf= o, > + u64 period_or_duty_cycle, u8 prescale) > { > - return min_t(u64, DIV_ROUND_DOWN_ULL(period_or_duty_cycle, 1 << (2 * pr= escale)), > + return min_t(u64, > + DIV_ROUND_DOWN_ULL(period_or_duty_cycle, > + 1 << (info->prescale_mult * prescale)), > U32_MAX); > } >=20 > @@ -262,6 +267,7 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_c= hip *chip, >=20 > { > struct rzg2l_gpt_chip *rzg2l_gpt =3D to_rzg2l_gpt_chip(chip); > + const struct rzg2l_gpt_info *info =3D rzg2l_gpt->info; > struct rzg2l_gpt_waveform *wfhw =3D _wfhw; > bool is_small_second_period =3D false; > u8 ch =3D RZG2L_GET_CH(pwm->hwpwm); > @@ -299,8 +305,8 @@ static int rzg2l_gpt_round_waveform_tohw(struct pwm_c= hip *chip, > } > } >=20 > - wfhw->prescale =3D rzg2l_gpt_calculate_prescale(period_ticks); > - pv =3D rzg2l_gpt_calculate_pv_or_dc(period_ticks, wfhw->prescale); > + wfhw->prescale =3D rzg2l_gpt_calculate_prescale(rzg2l_gpt, period_ticks= ); This is wrong here, as I dropped rzg2l_gpt in patch #3. Cheers, Biju