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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: bp.renesas.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TY3PR01MB11346.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: bd85a835-0eda-4d03-010a-08de4c48a976 X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Jan 2026 10:53:29.7592 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: x2jica9YLzJprZ66ybjG94F8I1BTDw2TD0uJ1zkKIrQ7vPuPDdWdR5f4yTUra4rNMVH2oGByRu+7dYfYhdvF4Tvr130G3Huhbo0XIFixhtc= X-MS-Exchange-Transport-CrossTenantHeadersStamped: OS7PR01MB17111 Hi Tommaso Merciai, > -----Original Message----- > From: Tommaso Merciai > Sent: 05 January 2026 10:50 > Subject: [PATCH v4 2/4] i3c: renesas: Store clock rate and reset controls= in struct renesas_i3c >=20 > Update the struct renesas_i3c to store the clock rate, presetn and treset= n handlers. Replace local > usage of the clock rate and reset controls with these structure fields. >=20 > Simplify the code and prepare the driver for upcoming suspend/resume supp= ort. >=20 > No functional change intended. >=20 > Reviewed-by: Frank Li > Signed-off-by: Tommaso Merciai > --- > v3->v4: > - No changes. >=20 > v2->v3: > - Collected FLi tag. > - Improved commit body. >=20 > v1->v2: > - New patch. >=20 > drivers/i3c/master/renesas-i3c.c | 39 ++++++++++++++++---------------- > 1 file changed, 20 insertions(+), 19 deletions(-) >=20 > diff --git a/drivers/i3c/master/renesas-i3c.c b/drivers/i3c/master/renesa= s-i3c.c > index 1b8f4be9ad67..7359f71f78dd 100644 > --- a/drivers/i3c/master/renesas-i3c.c > +++ b/drivers/i3c/master/renesas-i3c.c > @@ -258,11 +258,14 @@ struct renesas_i3c { > u32 free_pos; > u32 i2c_STDBR; > u32 i3c_STDBR; > + unsigned long rate; > u8 addrs[RENESAS_I3C_MAX_DEVS]; > struct renesas_i3c_xferqueue xferqueue; > void __iomem *regs; > struct clk_bulk_data *clks; > u8 num_clks; > + struct reset_control *presetn; > + struct reset_control *tresetn; Can this be above num_clks to avoid padding? Cheers, Biju > }; >=20 > struct renesas_i3c_i2c_dev_data { > @@ -482,22 +485,21 @@ static int renesas_i3c_bus_init(struct i3c_master_c= ontroller *m) > struct i3c_bus *bus =3D i3c_master_get_bus(m); > struct i3c_device_info info =3D {}; > struct i2c_timings t; > - unsigned long rate; > u32 double_SBR, val; > int cks, pp_high_ticks, pp_low_ticks, i3c_total_ticks; > int od_high_ticks, od_low_ticks, i2c_total_ticks; > int ret; >=20 > - rate =3D clk_get_rate(i3c->clks[RENESAS_I3C_TCLK_IDX].clk); > - if (!rate) > + i3c->rate =3D clk_get_rate(i3c->clks[RENESAS_I3C_TCLK_IDX].clk); > + if (!i3c->rate) > return -EINVAL; >=20 > ret =3D renesas_i3c_reset(i3c); > if (ret) > return ret; >=20 > - i2c_total_ticks =3D DIV_ROUND_UP(rate, bus->scl_rate.i2c); > - i3c_total_ticks =3D DIV_ROUND_UP(rate, bus->scl_rate.i3c); > + i2c_total_ticks =3D DIV_ROUND_UP(i3c->rate, bus->scl_rate.i2c); > + i3c_total_ticks =3D DIV_ROUND_UP(i3c->rate, bus->scl_rate.i3c); >=20 > i2c_parse_fw_timings(&m->dev, &t, true); >=20 > @@ -510,7 +512,7 @@ static int renesas_i3c_bus_init(struct i3c_master_con= troller *m) > pp_high_ticks =3D ((i3c_total_ticks * 5) / 10); > else > pp_high_ticks =3D DIV_ROUND_UP(I3C_BUS_THIGH_MIXED_MAX_NS, > - NSEC_PER_SEC / rate); > + NSEC_PER_SEC / i3c->rate); > pp_low_ticks =3D i3c_total_ticks - pp_high_ticks; >=20 > if ((od_low_ticks / 2) <=3D 0xFF && pp_low_ticks < 0x3F) @@ -518,7 +52= 0,7 @@ static int > renesas_i3c_bus_init(struct i3c_master_controller *m) >=20 > i2c_total_ticks /=3D 2; > i3c_total_ticks /=3D 2; > - rate /=3D 2; > + i3c->rate /=3D 2; > } >=20 > /* SCL clock period calculation in Open-drain mode */ @@ -539,8 +541,8 = @@ static int > renesas_i3c_bus_init(struct i3c_master_controller *m) > STDBR_SBRLP(pp_low_ticks) | > STDBR_SBRHP(pp_high_ticks); >=20 > - od_low_ticks -=3D t.scl_fall_ns / (NSEC_PER_SEC / rate) + 1; > - od_high_ticks -=3D t.scl_rise_ns / (NSEC_PER_SEC / rate) + 1; > + od_low_ticks -=3D t.scl_fall_ns / (NSEC_PER_SEC / i3c->rate) + 1; > + od_high_ticks -=3D t.scl_rise_ns / (NSEC_PER_SEC / i3c->rate) + 1; > i3c->i2c_STDBR =3D (double_SBR ? STDBR_DSBRPO : 0) | > STDBR_SBRLO(double_SBR, od_low_ticks) | > STDBR_SBRHO(double_SBR, od_high_ticks) | @@ -591,13 +593,13 @@ static= int > renesas_i3c_bus_init(struct i3c_master_controller *m) > renesas_set_bit(i3c->regs, SCSTRCTL, SCSTRCTL_ACKTWE); >=20 > /* Bus condition timing */ > - val =3D DIV_ROUND_UP(I3C_BUS_TBUF_MIXED_FM_MIN_NS, NSEC_PER_SEC / rate)= ; > + val =3D DIV_ROUND_UP(I3C_BUS_TBUF_MIXED_FM_MIN_NS, NSEC_PER_SEC / > +i3c->rate); > renesas_writel(i3c->regs, BFRECDT, BFRECDT_FRECYC(val)); >=20 > - val =3D DIV_ROUND_UP(I3C_BUS_TAVAL_MIN_NS, NSEC_PER_SEC / rate); > + val =3D DIV_ROUND_UP(I3C_BUS_TAVAL_MIN_NS, NSEC_PER_SEC / i3c->rate); > renesas_writel(i3c->regs, BAVLCDT, BAVLCDT_AVLCYC(val)); >=20 > - val =3D DIV_ROUND_UP(I3C_BUS_TIDLE_MIN_NS, NSEC_PER_SEC / rate); > + val =3D DIV_ROUND_UP(I3C_BUS_TIDLE_MIN_NS, NSEC_PER_SEC / i3c->rate); > renesas_writel(i3c->regs, BIDLCDT, BIDLCDT_IDLCYC(val)); >=20 > ret =3D i3c_master_get_free_addr(m, 0); > @@ -1300,7 +1302,6 @@ static const struct renesas_i3c_irq_desc renesas_i3= c_irqs[] =3D { static int > renesas_i3c_probe(struct platform_device *pdev) { > struct renesas_i3c *i3c; > - struct reset_control *reset; > int ret, i; >=20 > i3c =3D devm_kzalloc(&pdev->dev, sizeof(*i3c), GFP_KERNEL); @@ -1317,14= +1318,14 @@ static int > renesas_i3c_probe(struct platform_device *pdev) >=20 > i3c->num_clks =3D ret; >=20 > - reset =3D devm_reset_control_get_optional_exclusive_deasserted(&pdev->d= ev, "tresetn"); > - if (IS_ERR(reset)) > - return dev_err_probe(&pdev->dev, PTR_ERR(reset), > + i3c->tresetn =3D devm_reset_control_get_optional_exclusive_deasserted(&= pdev->dev, "tresetn"); > + if (IS_ERR(i3c->tresetn)) > + return dev_err_probe(&pdev->dev, PTR_ERR(i3c->tresetn), > "Error: missing tresetn ctrl\n"); >=20 > - reset =3D devm_reset_control_get_optional_exclusive_deasserted(&pdev->d= ev, "presetn"); > - if (IS_ERR(reset)) > - return dev_err_probe(&pdev->dev, PTR_ERR(reset), > + i3c->presetn =3D devm_reset_control_get_optional_exclusive_deasserted(&= pdev->dev, "presetn"); > + if (IS_ERR(i3c->presetn)) > + return dev_err_probe(&pdev->dev, PTR_ERR(i3c->presetn), > "Error: missing presetn ctrl\n"); >=20 > spin_lock_init(&i3c->xferqueue.lock); > -- > 2.43.0