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bh=IAj4Tgew2yQFSEbYTh7RBff5QH737OCKGA8Re8dFatY=; b=KidIQrayg8RhYHK5wwI83Kt7rmUBHK9TmDkCYa+7zM6b29JB34BxQOr9Io+PfsNhzbBbJU3shcl/x9ZhRTGWmuY5CzmsCjrwOTeenDQQwekv8AzoEMTLcsFIsMbK2MjFTKnfQ2nq6ImoOMYwhrEhoWnt/2XG74+bsu6iNISwD3I= Received: from TY3PR01MB11346.jpnprd01.prod.outlook.com (2603:1096:400:3d0::7) by TYCPR01MB7108.jpnprd01.prod.outlook.com (2603:1096:400:c3::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8699.24; Sun, 4 May 2025 12:53:25 +0000 Received: from TY3PR01MB11346.jpnprd01.prod.outlook.com ([fe80::86ef:ca98:234d:60e1]) by TY3PR01MB11346.jpnprd01.prod.outlook.com ([fe80::86ef:ca98:234d:60e1%4]) with mapi id 15.20.8699.022; Sun, 4 May 2025 12:53:25 +0000 From: Biju Das To: Prabhakar , Andrzej Hajda , Neil Armstrong , Robert Foss , laurent.pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel , Magnus Damm CC: "dri-devel@lists.freedesktop.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-renesas-soc@vger.kernel.org" , "linux-clk@vger.kernel.org" , Fabrizio Castro , Prabhakar Mahadev Lad Subject: RE: [PATCH v4 12/15] drm: renesas: rz-du: mipi_dsi: Add dphy_late_init() callback for RZ/V2H(P) Thread-Topic: [PATCH v4 12/15] drm: renesas: rz-du: mipi_dsi: Add dphy_late_init() callback for RZ/V2H(P) Thread-Index: AQHbuhBEHIXQ4f8QNEOzUP6Ud/smQrPCcsVw Date: Sun, 4 May 2025 12:53:25 +0000 Message-ID: References: <20250430204112.342123-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20250430204112.342123-13-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20250430204112.342123-13-prabhakar.mahadev-lad.rj@bp.renesas.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=bp.renesas.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: bp.renesas.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TY3PR01MB11346.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3eaf98ac-0488-4e7d-3c8f-08dd8b0aa8a7 X-MS-Exchange-CrossTenant-originalarrivaltime: 04 May 2025 12:53:25.1545 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 1/e7FRBoDtqcnz45blAvyInryKPqpxGImPko6jwqeqmGTdiiAVqCqZ2X/9UJT3DwpFFUXmuyM3nJssbGGh1Z+vIIOnfKuITbtOZiL7bm78w= X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYCPR01MB7108 Hi Prabhakar, Thanks for the patch. > -----Original Message----- > From: Prabhakar > Sent: 30 April 2025 21:41 > Subject: [PATCH v4 12/15] drm: renesas: rz-du: mipi_dsi: Add dphy_late_in= it() callback for RZ/V2H(P) >=20 > From: Lad Prabhakar >=20 > Introduce the `dphy_late_init` callback in `rzg2l_mipi_dsi_hw_info` to al= low additional D-PHY register > configurations after enabling data and clock lanes. This is required for = the RZ/V2H(P) SoC but not for > the RZ/G2L SoC. >=20 > Modify `rzg2l_mipi_dsi_startup()` to invoke `dphy_late_init` if defined, = ensuring SoC-specific > initialization is performed only when necessary. >=20 > This change prepares for RZ/V2H(P) SoC support while maintaining compatib= ility with existing > platforms. >=20 > Co-developed-by: Fabrizio Castro > Signed-off-by: Fabrizio Castro > Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Cheers, Biju > --- > v3->v4: > - No changes >=20 > v2->v3: > - No changes >=20 > v1->v2: > - No changes > --- > drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 4 ++++ > 1 file changed, 4 insertions(+) >=20 > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu= /drm/renesas/rz- > du/rzg2l_mipi_dsi.c > index 8c7384b95411..66eef39af35e 100644 > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > @@ -35,6 +35,7 @@ struct rzg2l_mipi_dsi; >=20 > struct rzg2l_mipi_dsi_hw_info { > int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, u64 hsfreq_millihz); > + void (*dphy_late_init)(struct rzg2l_mipi_dsi *dsi); > void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi); > u32 phy_reg_offset; > u32 link_reg_offset; > @@ -318,6 +319,9 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_d= si *dsi, > txsetr =3D TXSETR_DLEN | TXSETR_NUMLANEUSE(dsi->lanes - 1) | TXSETR_CLE= N; > rzg2l_mipi_dsi_link_write(dsi, TXSETR, txsetr); >=20 > + if (dsi->info->dphy_late_init) > + dsi->info->dphy_late_init(dsi); > + > hsfreq =3D DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, MILLI); > /* > * Global timings characteristic depends on high speed Clock Frequency > -- > 2.49.0