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bh=oe4HXKKDvts6EGBS8oLwx7LvK99rRMyohcjvDTc7Srg=; b=PjVfI+8YkzKi2kHCM4298m+2s+alO1VGO+d8GBw5vdfffCy/hegZq4sr2+WlKOcdBJG51bLaGlfjqPgQzW4tePs/HH18OcppcMcq573VxFOk3axXXl2GYOj1EJFQT4bAdMTuQjydqmrt1R7RyP6Wi3azmJl6wF0voPysfemjEyY= Received: from TY3PR01MB11346.jpnprd01.prod.outlook.com (2603:1096:400:3d0::7) by OSCPR01MB12626.jpnprd01.prod.outlook.com (2603:1096:604:33c::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8699.20; Sun, 4 May 2025 12:33:02 +0000 Received: from TY3PR01MB11346.jpnprd01.prod.outlook.com ([fe80::86ef:ca98:234d:60e1]) by TY3PR01MB11346.jpnprd01.prod.outlook.com ([fe80::86ef:ca98:234d:60e1%4]) with mapi id 15.20.8699.022; Sun, 4 May 2025 12:33:02 +0000 From: Biju Das To: Prabhakar , Andrzej Hajda , Neil Armstrong , Robert Foss , laurent.pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Michael Turquette , Stephen Boyd , Philipp Zabel , Magnus Damm CC: "dri-devel@lists.freedesktop.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-renesas-soc@vger.kernel.org" , "linux-clk@vger.kernel.org" , Fabrizio Castro , Prabhakar Mahadev Lad Subject: RE: [PATCH v4 08/15] drm: renesas: rz-du: mipi_dsi: Use VCLK for HSFREQ calculation Thread-Topic: [PATCH v4 08/15] drm: renesas: rz-du: mipi_dsi: Use VCLK for HSFREQ calculation Thread-Index: AQHbuhBCz0rjkP3SmUeE6uPVNrOVcbPCaOlw Date: Sun, 4 May 2025 12:33:01 +0000 Message-ID: References: <20250430204112.342123-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20250430204112.342123-9-prabhakar.mahadev-lad.rj@bp.renesas.com> In-Reply-To: <20250430204112.342123-9-prabhakar.mahadev-lad.rj@bp.renesas.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=bp.renesas.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: bp.renesas.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TY3PR01MB11346.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 80c1b86f-2144-4e47-912b-08dd8b07cf8b X-MS-Exchange-CrossTenant-originalarrivaltime: 04 May 2025 12:33:01.9519 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: T3mDWX+Fy6t/JzoIvobzLHsTrFfMOCeAd+eqvCvKPEgM5tGIBYU6ZboiBMKAGWF6sZT3m7Aba6rcQmk3jhHePOfMQaa71ft65GBHnnnveV4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: OSCPR01MB12626 Hi Prabhakar, > -----Original Message----- > From: Prabhakar > Sent: 30 April 2025 21:41 > Subject: [PATCH v4 08/15] drm: renesas: rz-du: mipi_dsi: Use VCLK for HSF= REQ calculation >=20 > From: Lad Prabhakar >=20 > Update the RZ/G2L MIPI DSI driver to calculate HSFREQ using the actual VC= LK rate instead of the mode > clock. The relationship between HSCLK and VCLK is: >=20 > vclk * bpp <=3D hsclk * 8 * lanes >=20 > Retrieve the VCLK rate using `clk_get_rate(dsi->vclk)`, ensuring that HSF= REQ accurately reflects the > clock rate set in hardware, leading to better precision in data transmiss= ion. >=20 > Additionally, use `DIV_ROUND_CLOSEST_ULL` for a more precise division whe= n computing `hsfreq`. Also, > update unit conversions to use correct scaling factors for better clarity= and correctness. >=20 > Since `clk_get_rate()` returns the clock rate in Hz, update the HSFREQ th= reshold comparisons to use Hz > instead of kHz to ensure correct behavior. >=20 > Co-developed-by: Fabrizio Castro > Signed-off-by: Fabrizio Castro > Signed-off-by: Lad Prabhakar > --- > v3->v4: > - Used MILLI instead of KILO >=20 > v2->v3: > - No changes >=20 > v1->v2: > - No changes > --- > .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 27 ++++++++++--------- > 1 file changed, 15 insertions(+), 12 deletions(-) >=20 > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu= /drm/renesas/rz- > du/rzg2l_mipi_dsi.c > index c5f698cd74f1..911c955a3a76 100644 > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > @@ -8,6 +8,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -15,6 +16,7 @@ > #include > #include > #include > +#include >=20 > #include > #include > @@ -199,7 +201,7 @@ static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi= _dsi *dsi, > /* All DSI global operation timings are set with recommended setting */ > for (i =3D 0; i < ARRAY_SIZE(rzg2l_mipi_dsi_global_timings); ++i) { > dphy_timings =3D &rzg2l_mipi_dsi_global_timings[i]; > - if (hsfreq <=3D dphy_timings->hsfreq_max) > + if (hsfreq <=3D (dphy_timings->hsfreq_max * MILLI)) > break; > } >=20 > @@ -258,7 +260,7 @@ static void rzg2l_mipi_dsi_dphy_exit(struct rzg2l_mip= i_dsi *dsi) static int > rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, > const struct drm_display_mode *mode) { > - unsigned long hsfreq; > + unsigned long hsfreq, vclk_rate; > unsigned int bpp; > u32 txsetr; > u32 clstptsetr; > @@ -269,6 +271,12 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_= dsi *dsi, > u32 golpbkt; > int ret; >=20 > + ret =3D pm_runtime_resume_and_get(dsi->dev); > + if (ret < 0) > + return ret; > + > + clk_set_rate(dsi->vclk, mode->clock * MILLI); > /* > * Relationship between hsclk and vclk must follow > * vclk * bpp =3D hsclk * 8 * lanes > @@ -280,13 +288,8 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_= dsi *dsi, > * hsclk(bit) =3D hsclk(byte) * 8 =3D hsfreq > */ > bpp =3D mipi_dsi_pixel_format_to_bpp(dsi->format); > - hsfreq =3D (mode->clock * bpp) / dsi->lanes; > - > - ret =3D pm_runtime_resume_and_get(dsi->dev); > - if (ret < 0) > - return ret; > - > - clk_set_rate(dsi->vclk, mode->clock * 1000); > + vclk_rate =3D clk_get_rate(dsi->vclk); Not sure, If there is a requested vclk for example, 108.45 MHz and get_rate= () is returning only 108MHz, do we need to propagate/print this error(like requested vs act= ual, if there is a mismatch) as there is change in resolution? Otherwise LGTM Reviewed-by: Biju Das Cheers, Biju > + hsfreq =3D DIV_ROUND_CLOSEST_ULL(vclk_rate * bpp, dsi->lanes); >=20 > ret =3D rzg2l_mipi_dsi_dphy_init(dsi, hsfreq); > if (ret < 0) > @@ -304,12 +307,12 @@ static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi= _dsi *dsi, > * - data lanes: maximum 4 lanes > * Therefore maximum hsclk will be 891 Mbps. > */ > - if (hsfreq > 445500) { > + if (hsfreq > 445500000) { > clkkpt =3D 12; > clkbfht =3D 15; > clkstpt =3D 48; > golpbkt =3D 75; > - } else if (hsfreq > 250000) { > + } else if (hsfreq > 250000000) { > clkkpt =3D 7; > clkbfht =3D 8; > clkstpt =3D 27; > @@ -753,7 +756,7 @@ static int rzg2l_mipi_dsi_probe(struct platform_devic= e *pdev) > * mode->clock and format are not available. So initialize DPHY with > * timing parameters for 80Mbps. > */ > - ret =3D rzg2l_mipi_dsi_dphy_init(dsi, 80000); > + ret =3D rzg2l_mipi_dsi_dphy_init(dsi, 80000000); > if (ret < 0) > goto err_phy; >=20 > -- > 2.49.0