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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: bp.renesas.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TY3PR01MB11346.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: bb885941-a790-4820-6fa0-08de88d03280 X-MS-Exchange-CrossTenant-originalarrivaltime: 23 Mar 2026 11:34:51.4715 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: YjS/2jYHKb/YHBGYPL31WJS5otxo++R9id7l4i8fG3gW2e3bzAUprQfcPMAmPXjKHuDLUXU3j8KtveeU1f6dcGPOie8czR20oRlqHKJq+FE= X-MS-Exchange-Transport-CrossTenantHeadersStamped: OSCPR01MB13180 Hi All, > -----Original Message----- > From: Biju > Sent: 22 March 2026 12:24 > Subject: [PATCH v6 15/15] irqchip/renesas-rzg2l: Add shared interrupt sup= port >=20 > From: Biju Das >=20 > The RZ/G3L SoC has 16 external interrupts, of which 8 are shared with TIN= T (GPIO interrupts), whereas > RZ/G2L has only 8 external interrupts with no sharing. The shared interru= pt line selection between > external interrupt and GPIO interrupt is based on the INTTSEL register. A= dd shared_irq_cnt variable to > struct rzg2l_hw_info handle these differences. >=20 > Add used_irqs bitmap to struct rzg2l_irqc_priv to track allocation state. > In the alloc callback, use test_and_set_bit() to enforce mutual exclusion= and configure the INTTSEL > register to route to either the external interrupt or TINT. In the free c= allback, use > test_and_clear_bit() to release the shared interrupt line and reset the I= NTTSEL. Also add INTTSEL > register save/restore support to the suspend/resume path. >=20 > Signed-off-by: Biju Das > --- > v5->v6: > * Updated commit description. > * Switched to using irq_domain_ops::{alloc,free} callbacks for mutual > exclusion between external interrupts and GPIO interrupts as using > irq_{request,release}_resources() leading to irq storm() > * Dropped irq_{request,release}_resources(). > * Replaced the macro TINTSEL->INTTSEL_TINTSEL > * Added macros INTTSEL_TINTSEL_START, IRQC_SHARED_IRQ_COUNT and > IRQC_IRQ_SHARED_START. > * Added used_irqs bitmap to struct rzg2l_irqc_priv to track allocation > state of shared_interrupt > * Added rzg2l_irqc_set_inttsel() for configuring INTTSEL register. > * Replaced irq_domain_free_irqs_common()->rzg2l_irqc_free() as > rzg2l_irqc_domain_ops::free() callback. > * Replaced the 8->IRQC_SHARED_IRQ_COUNT in shared_irq_cnt varaible as > the same macro used in bitmap. > v4->v5: > * Added callback irq_{request,release}_resources() to both irq and tint > interrupt chips. > v3->v4: > * Updated commit header irq->interrupt. > * Updated commit description IRQs->interrupts. > * Updated shared_irq_cnt variable type from u8->unsigned int. > v2->v3: > * No change > v1->v2: > * No change > --- > drivers/irqchip/irq-renesas-rzg2l.c | 104 +++++++++++++++++++++++++++- > 1 file changed, 103 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-re= nesas-rzg2l.c > index 1ff1c0efed66..97bbaaaeedb0 100644 > --- a/drivers/irqchip/irq-renesas-rzg2l.c > +++ b/drivers/irqchip/irq-renesas-rzg2l.c > @@ -22,6 +22,8 @@ >=20 > #define IRQC_IRQ_START 1 > #define IRQC_TINT_COUNT 32 > +#define IRQC_SHARED_IRQ_COUNT 8 > +#define IRQC_IRQ_SHARED_START (IRQC_IRQ_START + IRQC_SHARED_IRQ_COUNT) >=20 > #define ISCR 0x10 > #define IITSR 0x14 > @@ -29,6 +31,7 @@ > #define TITSR(n) (0x24 + (n) * 4) > #define TITSR0_MAX_INT 16 > #define TITSEL_WIDTH 0x2 > +#define INTTSEL 0x2c > #define TSSR(n) (0x30 + ((n) * 4)) > #define TIEN BIT(7) > #define TSSEL_SHIFT(n) (8 * (n)) > @@ -52,16 +55,21 @@ > #define IITSR_IITSEL_EDGE_BOTH 3 > #define IITSR_IITSEL_MASK(n) IITSR_IITSEL((n), 3) >=20 > +#define INTTSEL_TINTSEL(n) BIT(n) > +#define INTTSEL_TINTSEL_START 24 > + > #define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) > #define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) >=20 > /** > * struct rzg2l_irqc_reg_cache - registers cache (necessary for suspend/= resume) > * @iitsr: IITSR register > + * @inttsel: INTTSEL register > * @titsr: TITSR registers > */ > struct rzg2l_irqc_reg_cache { > u32 iitsr; > + u32 inttsel; > u32 titsr[2]; > }; >=20 > @@ -71,12 +79,14 @@ struct rzg2l_irqc_reg_cache { > * @irq_count: Number of IRQC interrupts > * @tint_start: Start of TINT interrupts > * @num_irq: Total Number of interrupts > + * @shared_irq_cnt: Number of shared interrupts > */ > struct rzg2l_hw_info { > const u8 *tssel_lut; > unsigned int irq_count; > unsigned int tint_start; > unsigned int num_irq; > + unsigned int shared_irq_cnt; > }; >=20 > /** > @@ -88,6 +98,7 @@ struct rzg2l_hw_info { > * @lock: Lock to serialize access to hardware registers > * @info: Hardware specific data > * @cache: Registers cache for suspend/resume > + * @used_irqs Bitmap to manage the shared interrupts > */ > static struct rzg2l_irqc_priv { > void __iomem *base; > @@ -97,6 +108,7 @@ static struct rzg2l_irqc_priv { > raw_spinlock_t lock; > struct rzg2l_hw_info info; > struct rzg2l_irqc_reg_cache cache; > + DECLARE_BITMAP(used_irqs, IRQC_SHARED_IRQ_COUNT); > } *rzg2l_irqc_data; >=20 > static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data) @= @ -464,6 +476,8 @@ static int > rzg2l_irqc_irq_suspend(void *data) > void __iomem *base =3D rzg2l_irqc_data->base; >=20 > cache->iitsr =3D readl_relaxed(base + IITSR); > + if (rzg2l_irqc_data->info.shared_irq_cnt) > + cache->inttsel =3D readl_relaxed(base + INTTSEL); > for (u8 i =3D 0; i < 2; i++) > cache->titsr[i] =3D readl_relaxed(base + TITSR(i)); >=20 > @@ -482,6 +496,8 @@ static void rzg2l_irqc_irq_resume(void *data) > */ > for (u8 i =3D 0; i < 2; i++) > writel_relaxed(cache->titsr[i], base + TITSR(i)); > + if (rzg2l_irqc_data->info.shared_irq_cnt) > + writel_relaxed(cache->inttsel, base + INTTSEL); > writel_relaxed(cache->iitsr, base + IITSR); } >=20 > @@ -562,6 +578,72 @@ static const struct irq_chip rzfive_irqc_tint_chip = =3D { > IRQCHIP_SKIP_SET_WAKE, > }; >=20 > +static bool rzg2l_irqc_is_shared_irqc(const struct rzg2l_hw_info info, > +unsigned int hw_irq) { > + return ((hw_irq >=3D (info.tint_start - info.shared_irq_cnt)) && hw_irq > +< info.tint_start); } > + > +static bool rzg2l_irqc_is_shared_tint(const struct rzg2l_hw_info info, > +unsigned int hw_irq) { > + return ((hw_irq >=3D (info.num_irq - info.shared_irq_cnt)) && hw_irq < > +info.num_irq); } > + > +static bool rzg2l_irq_is_shared_and_get_irq_num(struct rzg2l_irqc_priv *= priv, > + irq_hw_number_t hwirq, unsigned int *irq_num) { For consistency rzg2l_irqc_is_shared_and_get_irq_num() > + bool is_shared =3D false; > + > + if (rzg2l_irqc_is_shared_irqc(priv->info, hwirq)) { > + *irq_num =3D hwirq - IRQC_IRQ_SHARED_START; > + is_shared =3D true; > + } else if (rzg2l_irqc_is_shared_tint(priv->info, hwirq)) { > + *irq_num =3D hwirq - IRQC_TINT_COUNT - IRQC_IRQ_SHARED_START; > + is_shared =3D true; > + } > + > + return is_shared; > +} > + > +static void rzg2l_irqc_set_inttsel(struct rzg2l_irqc_priv *priv, unsigne= d int offset, > + unsigned int select_irq) > +{ > + u32 reg; > + > + guard(raw_spinlock)(&priv->lock); This may lead to dead lock, so need to use raw_spinlock_save. Driver probe and eoi handler executing on the same CPU. > + reg =3D readl_relaxed(priv->base + INTTSEL); > + if (select_irq) > + reg |=3D INTTSEL_TINTSEL(offset); > + else > + reg &=3D ~INTTSEL_TINTSEL(offset); > + writel_relaxed(reg, priv->base + INTTSEL); } > + > +static int rzg2l_irqc_shared_irq_alloc(struct rzg2l_irqc_priv *priv, > +irq_hw_number_t hwirq) { > + unsigned int irq_num; > + > + if (rzg2l_irq_is_shared_and_get_irq_num(priv, hwirq, &irq_num)) { > + if (test_and_set_bit(irq_num, priv->used_irqs)) > + return -EBUSY; > + > + if (hwirq < priv->info.tint_start) > + rzg2l_irqc_set_inttsel(priv, INTTSEL_TINTSEL_START + irq_num, 1); > + else > + rzg2l_irqc_set_inttsel(priv, INTTSEL_TINTSEL_START + irq_num, 0); > + } > + > + return 0; > +} > + > +static void rzg2l_irqc_shared_irq_free(struct rzg2l_irqc_priv *priv, > +irq_hw_number_t hwirq) { > + unsigned int irq_num; > + > + if (rzg2l_irq_is_shared_and_get_irq_num(priv, hwirq, &irq_num) && > + test_and_clear_bit(irq_num, priv->used_irqs)) > + rzg2l_irqc_set_inttsel(priv, INTTSEL_TINTSEL_START + irq_num, 0); } > + > static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq= , > unsigned int nr_irqs, void *arg) { @@ -594,6 +676,12 @@ static i= nt > rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq, > if (hwirq >=3D priv->info.num_irq) > return -EINVAL; >=20 > + if (priv->info.shared_irq_cnt) { > + ret =3D rzg2l_irqc_shared_irq_alloc(priv, hwirq); > + if (ret) > + return ret; > + } > + > ret =3D irq_domain_set_hwirq_and_chip(domain, virq, hwirq, chip, (void = *)(uintptr_t)tint); > if (ret) > return ret; If this fails, rzg2l_irqc_shared_irq_free() to be called. I will fix this in next version. Cheers, Biju