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From: Shiji Yang <yangshiji66@outlook.com>
To: sergio.paracuellos@gmail.com
Cc: arinc.unal@arinc9.com, devicetree@vger.kernel.org,
	john@phrozen.org, krzysztof.kozlowski+dt@linaro.org,
	linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-mips@vger.kernel.org, matthias.bgg@gmail.com,
	mturquette@baylibre.com, p.zabel@pengutronix.de,
	robh+dt@kernel.org, sboyd@kernel.org, tsbogend@alpha.franken.de,
	yangshiji66@outlook.com
Subject: Re: [PATCH v3 2/9] clk: ralink: add clock and reset driver for MTMIPS SoCs
Date: Sat, 17 Jun 2023 13:50:52 +0800	[thread overview]
Message-ID: <TYAP286MB0315C2088627FB035A5D43D6BC59A@TYAP286MB0315.JPNP286.PROD.OUTLOOK.COM> (raw)
In-Reply-To: <CAMhs-H_GjHU+r33oeytXiyu+bgGTrGL8Ck=DbsMYnqC-XBNYYw@mail.gmail.com>

Thank you for your quick reply!

>> >+      {
>> >+              .compatible = "ralink,mt7620a-sysc",
>> >+              .data = &mt7620_clk_data,
>> >+      },
>> >+      {
>> >+              .compatible = "ralink,mt7620-sysc",
>> >+              .data = &mt7620_clk_data,
>> >+      },
>> >+      {
>>
>> I am confused about the difference between `ralink,mt7620-sysc` and
>> `ralink,mt7620a-sysc`. Do you mean mt7620n?
>> https://www.mediatek.com/products/home-networking/mt7620n-a
>
>There is no real difference. As you can see both of them use the same
>'mt7620_clk_data' but since both compatible strings already exist
>somewhere I introduced both of them.
>

If they are the same, perhaps `mt7620a` also need to be checked in mtmips_clk_regs_init().
Or just remove compatible string of `mt7620a` and update dtsi files?

>+static void __init mtmips_clk_regs_init(struct device_node *node,
>+					struct mtmips_clk_priv *priv)
>+{
>+	u32 t;
>+
>+	if (!of_device_is_compatible(node, "ralink,mt7620-sysc"))
>+		return;
>+
>+	/*
>+	 * When the CPU goes into sleep mode, the BUS
>+	 * clock will be too low for USB to function properly.
>+	 * Adjust the busses fractional divider to fix this
>+	 */
>+	regmap_read(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, &t);
>+	t &= ~(CLKCFG_FDIV_MASK | CLKCFG_FFRAC_MASK);
>+	t |= CLKCFG_FDIV_USB_VAL | CLKCFG_FFRAC_USB_VAL;
>+	regmap_write(priv->sysc, SYSC_REG_CPU_SYS_CLKCFG, t);
>+}
>+

If we choose to update dts file. We can also remove the legacy
"ralink,rt2880-reset" compatible string by the way.

>+static const struct of_device_id mtmips_clk_of_match[] = {
>+	{ .compatible = "ralink,rt2880-reset" },
>+	{ .compatible = "ralink,rt2880-sysc" },
>+	{ .compatible = "ralink,rt3050-sysc" },
>+	{ .compatible = "ralink,rt3050-sysc" },
>+	{ .compatible = "ralink,rt3352-sysc" },
>+	{ .compatible = "ralink,rt3883-sysc" },
>+	{ .compatible = "ralink,rt5350-sysc" },
>+	{ .compatible = "ralink,mt7620a-sysc" },
>+	{ .compatible = "ralink,mt7620-sysc" },
>+	{ .compatible = "ralink,mt7628-sysc" },
>+	{ .compatible = "ralink,mt7688-sysc" },
>+	{}
>+};

Thanks,
    Shiji Yang

  reply	other threads:[~2023-06-17  5:51 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-18  9:03 [PATCH v3 0/9] mips: ralink: add complete clock and reset driver for mtmips SoCs Sergio Paracuellos
2023-04-18  9:03 ` [PATCH v3 1/9] dt-bindings: clock: add mtmips SoCs system controller Sergio Paracuellos
2023-04-21 18:00   ` Rob Herring
2023-06-16 18:03   ` Stephen Boyd
2023-04-18  9:03 ` [PATCH v3 2/9] clk: ralink: add clock and reset driver for MTMIPS SoCs Sergio Paracuellos
2023-06-16 18:03   ` Stephen Boyd
2023-06-17  4:51   ` yangshiji66
2023-06-17  5:06     ` Sergio Paracuellos
2023-06-17  5:50       ` Shiji Yang [this message]
2023-06-17  6:00         ` Sergio Paracuellos
2023-04-18  9:03 ` [PATCH v3 3/9] mips: ralink: rt288x: remove clock related code Sergio Paracuellos
2023-04-18  9:03 ` [PATCH v3 4/9] mips: ralink: rt305x: " Sergio Paracuellos
2023-04-18  9:03 ` [PATCH v3 5/9] mips: ralink: rt3883: " Sergio Paracuellos
2023-04-18  9:03 ` [PATCH v3 6/9] mips: ralink: mt7620: " Sergio Paracuellos
2023-04-18  9:03 ` [PATCH v3 7/9] mips: ralink: remove reset " Sergio Paracuellos
2023-04-18  9:03 ` [PATCH v3 8/9] mips: ralink: get cpu rate from new driver code Sergio Paracuellos
2023-04-18  9:03 ` [PATCH v3 9/9] MAINTAINERS: add Mediatek MTMIPS Clock maintainer Sergio Paracuellos
2023-05-04 14:48 ` [PATCH v3 0/9] mips: ralink: add complete clock and reset driver for mtmips SoCs Sergio Paracuellos
2023-05-23  9:47   ` Sergio Paracuellos
2023-06-16  6:12     ` Sergio Paracuellos
2023-06-16  6:47       ` Thomas Bogendoerfer
2023-06-17  5:24 [PATCH v4 2/9] clk: ralink: add clock and reset driver for MTMIPS SoCs Sergio Paracuellos
2023-06-17 12:54 ` [PATCH v3 " Shiji Yang
2023-06-17 13:07   ` Krzysztof Kozlowski
2023-06-17 13:31     ` Sergio Paracuellos
2023-06-17 14:43       ` Krzysztof Kozlowski
2023-06-17 15:37         ` Sergio Paracuellos
2023-06-17 17:20           ` Krzysztof Kozlowski
2023-06-17 19:11             ` Sergio Paracuellos
2023-06-18  5:04               ` Sergio Paracuellos
2023-06-17 13:26   ` Sergio Paracuellos
2023-06-17 14:43     ` Krzysztof Kozlowski
2023-06-17 15:31       ` Sergio Paracuellos

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