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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: bp.renesas.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: TYCPR01MB11332.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8adcd3a1-a63b-41bb-6917-08de16021bc4 X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Oct 2025 09:12:24.4548 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: WpxN6Ptv1w+1jobK9dcd1rf7st2+mS3Emuyn9DvvuUR11a/UoIxo1Thth+jFZAB3Tosv8xPtzValOp6GrrueNKn14QNqe/wvzsXLiPFovVM= X-MS-Exchange-Transport-CrossTenantHeadersStamped: TY4PR01MB14072 Hi Greg, Thanks for the feedback. > -----Original Message----- > From: Greg Kroah-Hartman > Sent: 28 October 2025 08:42 > Subject: Re: [PATCH 00/19] Add RZ/G3E RSCI support >=20 > On Mon, Oct 27, 2025 at 03:45:47PM +0000, Biju Das wrote: > > Add RZ/G3E RSCI support for FIFO and non-FIFO mode. RSCI IP found on > > RZ/G3E SoC is similar to one on RZ/T2H, but has 32-stage fifo. RZ/G3E > > has > > 5 module clocks compared to 2 on RZ/T2H, and it has multiple resets. > > Add support for hardware flow control. > > > > Biju Das (19): > > clk: renesas: r9a09g047: Add RSCI clocks/resets >=20 > Why is a clk patch part of a serial series? How are we supposed to merge= this thing? OK, will split the series into clock, driver fix, dt-binding fix ,=20 dt-binding + driver patches for the next and dts patches. Cheers, Biju