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Kind regards, Fab > From: Fabrizio Castro > Sent: 05 March 2025 00:21 > Subject: [PATCH v5 5/6] dmaengine: sh: rz-dmac: Add RZ/V2H(P) support >=20 > The DMAC IP found on the Renesas RZ/V2H(P) family of SoCs is > similar to the version found on the Renesas RZ/G2L family of > SoCs, but there are some differences: > * It only uses one register area > * It only uses one clock > * It only uses one reset > * Instead of using MID/IRD it uses REQ No > * It is connected to the Interrupt Control Unit (ICU) > * On the RZ/G2L there is only 1 DMAC, on the RZ/V2H(P) there are 5 >=20 > Add specific support for the Renesas RZ/V2H(P) family of SoC by > tackling the aforementioned differences. >=20 > Signed-off-by: Fabrizio Castro > --- > v4->v5: > * Reused RZ/G2L cell specification (with REQ No in place of MID/RID). > * Dropped ACK No. > * Removed mid_rid/req_no/ack_no union and reused mid_rid for REQ No. > * Other small improvements. > v3->v4: > * Fixed an issue with mid_rid/req_no/ack_no initialization > v2->v3: > * Dropped change to Kconfig. > * Replaced rz_dmac_type with has_icu flag. > * Put req_no and ack_no in an anonymous struct, nested under an > anonymous union with mid_rid. > * Dropped data field of_rz_dmac_match[], and added logic to determine > value of has_icu flag from DT parsing. > v1->v2: > * Switched to new macros for minimum values. > --- > drivers/dma/sh/rz-dmac.c | 81 ++++++++++++++++++++++++++++++++++++---- > 1 file changed, 74 insertions(+), 7 deletions(-) >=20 > diff --git a/drivers/dma/sh/rz-dmac.c b/drivers/dma/sh/rz-dmac.c > index d7a4ce28040b..1f687b08d6b8 100644 > --- a/drivers/dma/sh/rz-dmac.c > +++ b/drivers/dma/sh/rz-dmac.c > @@ -14,6 +14,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -89,8 +90,14 @@ struct rz_dmac_chan { >=20 > #define to_rz_dmac_chan(c) container_of(c, struct rz_dmac_chan, vc.chan) >=20 > +struct rz_dmac_icu { > + struct platform_device *pdev; > + u8 dmac_index; > +}; > + > struct rz_dmac { > struct dma_device engine; > + struct rz_dmac_icu icu; > struct device *dev; > struct reset_control *rstc; > void __iomem *base; > @@ -99,6 +106,8 @@ struct rz_dmac { > unsigned int n_channels; > struct rz_dmac_chan *channels; >=20 > + bool has_icu; > + > DECLARE_BITMAP(modules, 1024); > }; >=20 > @@ -167,6 +176,9 @@ struct rz_dmac { > #define RZ_DMAC_MAX_CHANNELS 16 > #define DMAC_NR_LMDESC 64 >=20 > +/* RZ/V2H ICU related */ > +#define RZV2H_MAX_DMAC_INDEX 4 > + > /* > * ---------------------------------------------------------------------= -------- > * Device access > @@ -324,7 +336,13 @@ static void rz_dmac_prepare_desc_for_memcpy(struct r= z_dmac_chan *channel) > lmdesc->chext =3D 0; > lmdesc->header =3D HEADER_LV; >=20 > - rz_dmac_set_dmars_register(dmac, channel->index, 0); > + if (dmac->has_icu) { > + rzv2h_icu_register_dma_req(dmac->icu.pdev, dmac->icu.dmac_index, > + channel->index, > + RZV2H_ICU_DMAC_REQ_NO_DEFAULT); > + } else { > + rz_dmac_set_dmars_register(dmac, channel->index, 0); > + } >=20 > channel->chcfg =3D chcfg; > channel->chctrl =3D CHCTRL_STG | CHCTRL_SETEN; > @@ -375,7 +393,13 @@ static void rz_dmac_prepare_descs_for_slave_sg(struc= t rz_dmac_chan *channel) >=20 > channel->lmdesc.tail =3D lmdesc; >=20 > - rz_dmac_set_dmars_register(dmac, channel->index, channel->mid_rid); > + if (dmac->has_icu) { > + rzv2h_icu_register_dma_req(dmac->icu.pdev, dmac->icu.dmac_index, > + channel->index, channel->mid_rid); > + } else { > + rz_dmac_set_dmars_register(dmac, channel->index, channel->mid_rid); > + } > + > channel->chctrl =3D CHCTRL_SETEN; > } >=20 > @@ -647,7 +671,13 @@ static void rz_dmac_device_synchronize(struct dma_ch= an *chan) > if (ret < 0) > dev_warn(dmac->dev, "DMA Timeout"); >=20 > - rz_dmac_set_dmars_register(dmac, channel->index, 0); > + if (dmac->has_icu) { > + rzv2h_icu_register_dma_req(dmac->icu.pdev, dmac->icu.dmac_index, > + channel->index, > + RZV2H_ICU_DMAC_REQ_NO_DEFAULT); > + } else { > + rz_dmac_set_dmars_register(dmac, channel->index, 0); > + } > } >=20 > /* > @@ -824,6 +854,38 @@ static int rz_dmac_chan_probe(struct rz_dmac *dmac, > return 0; > } >=20 > +static int rz_dmac_parse_of_icu(struct device *dev, struct rz_dmac *dmac= ) > +{ > + struct device_node *np =3D dev->of_node; > + struct of_phandle_args args; > + uint32_t dmac_index; > + int ret; > + > + ret =3D of_parse_phandle_with_fixed_args(np, "renesas,icu", 1, 0, &args= ); > + if (ret =3D=3D -ENOENT) > + return 0; > + if (ret) > + return ret; > + > + dmac->has_icu =3D true; > + > + dmac->icu.pdev =3D of_find_device_by_node(args.np); > + of_node_put(args.np); > + if (!dmac->icu.pdev) { > + dev_err(dev, "ICU device not found.\n"); > + return -ENODEV; > + } > + > + dmac_index =3D args.args[0]; > + if (dmac_index > RZV2H_MAX_DMAC_INDEX) { > + dev_err(dev, "DMAC index %u invalid.\n", dmac_index); > + return -EINVAL; > + } > + dmac->icu.dmac_index =3D dmac_index; > + > + return 0; > +} > + > static int rz_dmac_parse_of(struct device *dev, struct rz_dmac *dmac) > { > struct device_node *np =3D dev->of_node; > @@ -840,7 +902,7 @@ static int rz_dmac_parse_of(struct device *dev, struc= t rz_dmac *dmac) > return -EINVAL; > } >=20 > - return 0; > + return rz_dmac_parse_of_icu(dev, dmac); > } >=20 > static int rz_dmac_probe(struct platform_device *pdev) > @@ -874,9 +936,11 @@ static int rz_dmac_probe(struct platform_device *pde= v) > if (IS_ERR(dmac->base)) > return PTR_ERR(dmac->base); >=20 > - dmac->ext_base =3D devm_platform_ioremap_resource(pdev, 1); > - if (IS_ERR(dmac->ext_base)) > - return PTR_ERR(dmac->ext_base); > + if (!dmac->has_icu) { > + dmac->ext_base =3D devm_platform_ioremap_resource(pdev, 1); > + if (IS_ERR(dmac->ext_base)) > + return PTR_ERR(dmac->ext_base); > + } >=20 > /* Register interrupt handler for error */ > irq =3D platform_get_irq_byname(pdev, irqname); > @@ -991,9 +1055,12 @@ static void rz_dmac_remove(struct platform_device *= pdev) > reset_control_assert(dmac->rstc); > pm_runtime_put(&pdev->dev); > pm_runtime_disable(&pdev->dev); > + > + platform_device_put(dmac->icu.pdev); > } >=20 > static const struct of_device_id of_rz_dmac_match[] =3D { > + { .compatible =3D "renesas,r9a09g057-dmac", }, > { .compatible =3D "renesas,rz-dmac", }, > { /* Sentinel */ } > }; > -- > 2.34.1