RE: [PATCH v4 3/7] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs

[Fabrizio Castro <fabrizio.castro.jz@renesas.com>]

Hi Geert,

Thanks for your feedback!

> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 28 February 2025 15:16
> Subject: Re: [PATCH v4 3/7] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs
> 
> Hi Fabrizio,
> 
> On Fri, 28 Feb 2025 at 15:55, Fabrizio Castro
> <fabrizio.castro.jz@renesas.com> wrote:
> > > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > > Sent: 28 February 2025 10:17
> > > Subject: Re: [PATCH v4 3/7] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs
> > >
> > > Hi Fabrizio,
> > >
> > > On Thu, 27 Feb 2025 at 19:16, Fabrizio Castro
> > > <fabrizio.castro.jz@renesas.com> wrote:
> > > > > From: Geert Uytterhoeven <geert@linux-m68k.org>
> > > > > Sent: 24 February 2025 12:44
> > > > > Subject: Re: [PATCH v4 3/7] dt-bindings: dma: rz-dmac: Document RZ/V2H(P) family of SoCs
> > > > >
> > > > > On Thu, 20 Feb 2025 at 16:01, Fabrizio Castro
> > > > > <fabrizio.castro.jz@renesas.com> wrote:
> > > > > > Document the Renesas RZ/V2H(P) family of SoCs DMAC block.
> > > > > > The Renesas RZ/V2H(P) DMAC is very similar to the one found on the
> > > > > > Renesas RZ/G2L family of SoCs, but there are some differences:
> > > > > > * It only uses one register area
> > > > > > * It only uses one clock
> > > > > > * It only uses one reset
> > > > > > * Instead of using MID/IRD it uses REQ NO/ACK NO
> > > > > > * It is connected to the Interrupt Control Unit (ICU)
> > > > > >
> > > > > > Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com>
> > > > >
> > > > > > v1->v2:
> > > > > > * Removed RZ/V2H DMAC example.
> > > > > > * Improved the readability of the `if` statement.
> > > > >
> > > > > Thanks for the update!
> > > > >
> > > > > > --- a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > > > > > +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> > > > > > @@ -61,14 +66,22 @@ properties:
> > > > > >    '#dma-cells':
> > > > > >      const: 1
> > > > > >      description:
> > > > > > -      The cell specifies the encoded MID/RID values of the DMAC port
> > > > > > -      connected to the DMA client and the slave channel configuration
> > > > > > -      parameters.
> > > > > > +      For the RZ/A1H, RZ/Five, RZ/G2{L,LC,UL}, RZ/V2L, and RZ/G3S SoCs, the cell
> > > > > > +      specifies the encoded MID/RID values of the DMAC port connected to the
> > > > > > +      DMA client and the slave channel configuration parameters.
> > > > > >        bits[0:9] - Specifies MID/RID value
> > > > > >        bit[10] - Specifies DMA request high enable (HIEN)
> > > > > >        bit[11] - Specifies DMA request detection type (LVL)
> > > > > >        bits[12:14] - Specifies DMAACK output mode (AM)
> > > > > >        bit[15] - Specifies Transfer Mode (TM)
> > > > > > +      For the RZ/V2H(P) SoC the cell specifies the REQ NO, the ACK NO, and the
> > > > > > +      slave channel configuration parameters.
> > > > > > +      bits[0:9] - Specifies the REQ NO
> > > > >
> > > > > So REQ_NO is the new name for MID/RID.
> > >
> > > These are documented in Table 4.7-22 ("DMA Transfer Request Detection
> > > Operation Setting Table").
> >
> > REQ_NO is documented in both Table 4.7-22 and in Table 4.6-23 (column `DMAC No.`).
> 
> Indeed. But not for all of them. E.g. RSPI is missing, IIC is present.

I can see the RSPI related `REQ No.` in the version of the manual I am using,
although one must be very careful to look at the right entry in the table,
as the table is quite big, and the entries are ordered by `SPI No.`.

For some devices, the SPI numbers are not contiguous therefore the device specific
bits may end up scattered.
For example, for `Name` `RSPI_CH0_sp_rxintpls_n` (mind that the `pls_n` substring
is on a new line in the table) you can see from Table 4.6-23 that
its `DMAC No.` is 140 (as you said, in decimal...).

> And the numbers are shown in decimal instead of in hex ;-)
> 
> > > > It's certainly similar. I would say that REQ_NO + ACK_NO is the new MID_RID.
> > > >
> > > > > > +      bits[10:16] - Specifies the ACK NO
> > > > >
> > > > > This is a new field.
> > > > > However, it is not clear to me which value to specify here, and if this
> > > > > is a hardware property at all, and thus needs to be specified in DT?
> > > >
> > > > It is a HW property. The value to set can be found in Table 4.6-27 from
> > > > the HW User Manual, column "Ack No".
> > >
> > > Thanks, but that table only shows values for SPDIF, SCU, SSIU and PFC
> > > (for external DMA requests).  The most familiar DMA clients listed
> > > in Table 4.7-22 are missing.  E.g. RSPI0 uses REQ_NO 0x8C/0x8D, but
> > > which values does it need for ACK_NO?
> >
> > Only a handful of devices need it. For every other device (and use case) only the
> > default value is needed.
> 
> The default value is RZV2H_ICU_DMAC_ACK_NO_DEFAULT = 0x7f?

Yes.

Thanks!

Fab


> Which I believe already causes you to run into the out-of-range DMACKSELk
> register offset in rzv2h_icu_register_dma_req_ack()?
> 
> > But I'll take this out for now, until we get to support a device that actually
> > needs ACK NO.
> 
> OK.
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds