From: Ziyang Huang <hzyitc@outlook.com>
To: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: richard@nod.at, vigneshr@ti.com, tudor.ambarus@linaro.org,
mmkurbanov@salutedevices.com, george.moussalem@outlook.com,
linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] Revert "mtd: spinand: esmt: fix id code for F50D1G41LB"
Date: Fri, 12 Dec 2025 22:53:31 +0800 [thread overview]
Message-ID: <TYZPR01MB55568ED405DCABFB5A4BD503C9AEA@TYZPR01MB5556.apcprd01.prod.exchangelabs.com> (raw)
In-Reply-To: <87wm2x74pz.fsf@bootlin.com>
在 2025/12/8 16:33, Miquel Raynal 写道:
> On 02/12/2025 at 23:05:56 +08, Ziyang Huang <hzyitc@outlook.com> wrote:
>
>> This reverts commit dd26402642a0899fde59ea6b0852fad3d799b4cc.
>>
>> The issue George met is due to the limit of QPIC, not the issue of the
>> flash chip.
>>
>> QPIC only supports 4 bytes ID. So the fifth byte is always 0.
>>
>> If we use spi-gpio, the fifth byte can be read correctly.
>>
>> Signed-off-by: Ziyang Huang <hzyitc@outlook.com>
>> ---
>
> So how do we solve that?
>
> Is there anything than can be done on the qpic side?
>
> Thanks,
> Miquèl
Unfortunately, There is not a good way to solve it now.
In Openwrt, I made a hack to force the max compare bytes to 4.
I'm trying to find a way to let QPIC do a raw SPI op. But without
documents, it's hard.
For router devices, an other typical way is to use parameter page. This
feature is supported in almost all of the high-speed QSPI NANDs they used.
But for now, 4 bytes is enough for the router devices since only a few
flash models will be used. More the that, some vendor SDKs use 2 bytes.
next prev parent reply other threads:[~2025-12-12 14:53 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-02 15:05 Ziyang Huang
2025-12-08 8:33 ` Miquel Raynal
2025-12-08 9:26 ` George Moussalem
2025-12-08 10:26 ` Md Sadre Alam
2025-12-16 8:07 ` Miquel Raynal
2025-12-12 14:53 ` Ziyang Huang [this message]
2025-12-16 8:09 ` Miquel Raynal
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