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qca8k: add internal-PHY-to-PHY CPU link example To: Andrew Lunn Cc: olteanv@gmail.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, rmk+kernel@armlinux.org.uk, javier.carrasco.cruz@gmail.com, john@phrozen.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <55a2e7d3-f201-48d7-be4e-5d1307e52f56@lunn.ch> From: Ziyang Huang In-Reply-To: <55a2e7d3-f201-48d7-be4e-5d1307e52f56@lunn.ch> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: SI2PR06CA0009.apcprd06.prod.outlook.com (2603:1096:4:186::17) To TYZPR01MB5556.apcprd01.prod.exchangelabs.com (2603:1096:400:363::9) X-Microsoft-Original-Message-ID: <3fff1fba-2631-49b8-b419-f0e4f3aa8646@outlook.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 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X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Mar 2025 05:01:13.7195 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-Transport-CrossTenantHeadersStamped: SEZPR01MB5422 在 2025/3/4 1:15, Andrew Lunn 写道: > On Tue, Mar 04, 2025 at 12:37:36AM +0800, Ziyang Huang wrote: >> 在 2025/3/4 0:15, Andrew Lunn 写道: >>> ... >>> >>> The previous patch still causes it to look at port 0 and then port 6 >>> first. Only if they are not CPU ports will it look at other ports. So >>> this example does not work, port 6 will be the CPU port, even with the >>> properties you added. >> >> Sorry, I forget that the following patch is still penging: >> https://lore.kernel.org/all/20230620063747.19175-1-ansuelsmth@gmail.com/ >> >> With this path, we can have multi CPU link. > > So you should get that merged first. Then this patch. After checking the code again, the demo 2 has already had 2 CPU link (Port0 and Port6). Could I just keep this or should I need to add a new case ? >>> When you fix this, i also think it would be good to extend: >>> >>>> + /* PHY-to-PHY CPU link */ >>> >>> with the work internal. >>> >>> This also seems an odd architecture to me. If this is SoC internal, >>> why not do a MAC to MAC link? What benefit do you get from having the >>> PHYs? >> >> This patches are for IPQ50xx platform which has only one a SGMII/SGMII+ link >> and a MDI link. >> >> It has 2 common designs: >> 1. SGMII+ is used to connect a 2.5G PHY, which make qca8337 only be able to >> be connected through the MDI link. > > Please do not call it SGMII+. It is not SGMII if it is running at > 2.5G. It is more likely to be broken 2500BaseX, broken in that it does > not implement the inband signalling. > >> 2. Both SGMII and MDI links are used to connect the qca8337, so we can get >> 2G link which is beneficial in NAT mode (total 2G bidirectional). > > So is this actually internally? Or do you have a IPQ50xx SoC connected > to a qca8337 switch, with copper traces on a PCB? If so, it is not > internal. I think I known which point you are confused about. Sorry for my poor English. The "internal" is used to describe the localcation of PHY not the link. In current code, qca8k has supported to use a external PHY to do a PHY-to-PHY link (Port0 and Port6). This patch make the internal PHYs support it too (Port1-5). The followiing topology is existed in most IPQ50xx-based router: _______________________ _______________________ | IPQ5018 | | QCA8337 | | +------+ +--------+ | | +--------+ +------+ | | | MAC0 |---| GE Phy |-+--MDI--+-| Phy4 |---| MAC5 | | | +------+ +--------+ | | +--------+ +------+ | | +------+ +--------+ | | +--------+ +------+ | | | MAC1 |---| Uniphy |-+-SGMII-+-| SerDes |---| MAC0 | | | +------+ +--------+ | | +--------+ +------+ | |_______________________| |_______________________| > Andrew