From: Ziyang Huang <hzyitc@outlook.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: "olteanv@gmail.com" <olteanv@gmail.com>,
"davem@davemloft.net" <davem@davemloft.net>,
"edumazet@google.com" <edumazet@google.com>,
"kuba@kernel.org" <kuba@kernel.org>,
"pabeni@redhat.com" <pabeni@redhat.com>,
"robh@kernel.org" <robh@kernel.org>,
"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
"conor+dt@kernel.org" <conor+dt@kernel.org>,
"rmk+kernel@armlinux.org.uk" <rmk+kernel@armlinux.org.uk>,
"javier.carrasco.cruz@gmail.com" <javier.carrasco.cruz@gmail.com>,
"john@phrozen.org" <john@phrozen.org>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/2] dt-bindings: net: dsa: qca8k: add internal-PHY-to-PHY CPU link example
Date: Wed, 5 Mar 2025 22:41:00 +0800 [thread overview]
Message-ID: <TYZPR01MB5556CB47BC21C5015F698CA4C9CB2@TYZPR01MB5556.apcprd01.prod.exchangelabs.com> (raw)
In-Reply-To: <f7ac97f4-7677-402d-99f1-ae82709a3549@lunn.ch>
在 2025/3/4 22:11, Andrew Lunn 写道:
>> (Port0 and Port6). Could I just keep this or should I need to add a new
>> case ?
>
> The existing examples are probably sufficient. Just check the text to
> make sure it does not limit it to ports 0 and 6.
>
>>> So is this actually internally? Or do you have a IPQ50xx SoC connected
>>> to a qca8337 switch, with copper traces on a PCB? If so, it is not
>>> internal.
>>
>> The "internal" is used to describe the localcation of PHY not the link.
>> In current code, qca8k has supported to use a external PHY to do a
>> PHY-to-PHY link (Port0 and Port6). This patch make the internal PHYs
>> support it too (Port1-5).
>>
>> The followiing topology is existed in most IPQ50xx-based router:
>> _______________________ _______________________
>> | IPQ5018 | | QCA8337 |
>> | +------+ +--------+ | | +--------+ +------+ |
>> | | MAC0 |---| GE Phy |-+--MDI--+-| Phy4 |---| MAC5 | |
>> | +------+ +--------+ | | +--------+ +------+ |
>> | +------+ +--------+ | | +--------+ +------+ |
>> | | MAC1 |---| Uniphy |-+-SGMII-+-| SerDes |---| MAC0 | |
>> | +------+ +--------+ | | +--------+ +------+ |
>> |_______________________| |_______________________|
>
> So logically, it does not matter if the PHY is internal or
> external. The patch would be the same. I've even see setups where the
> SGMII link would have a PHY, then a connection to a daughter board,
> and then a PHY back to SGMII before connecting to the switch. Running
> Ethernet over the connector is easier than SERDES lines.
>
> So i would probably drop the word internal from this discussion,
> unless it is really relevant.
>
> Andrew
Ok, will remove the word in next patch
prev parent reply other threads:[~2025-03-05 14:41 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-03 15:22 [PATCH 0/2] net: dsa: qca8k: support internal-PHY-to-PHY CPU link Ziyang Huang
2025-03-03 15:24 ` [PATCH 1/2] " Ziyang Huang
2025-03-03 15:24 ` [PATCH 2/2] dt-bindings: net: dsa: qca8k: add internal-PHY-to-PHY CPU link example Ziyang Huang
2025-03-03 16:15 ` Andrew Lunn
2025-03-03 16:37 ` Ziyang Huang
2025-03-03 17:15 ` Andrew Lunn
2025-03-04 5:00 ` Ziyang Huang
[not found] ` <dbd0e376-d7c3-4ba9-886b-ba9529a2ec4e@outlook.com>
2025-03-04 14:11 ` Andrew Lunn
2025-03-05 14:41 ` Ziyang Huang [this message]
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