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invalidations To: fangyu.yu@linux.alibaba.com, tomasz.jeznach@linux.dev, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, baolu.lu@linux.intel.com, jroedel@suse.de, zong.li@sifive.com, andrew.jones@linux.dev, anup@brainfault.org, jgg@nvidia.com, jgg@ziepe.ca, kevin.tian@intel.com, atish.patra@linux.dev, skhawaja@google.com, vasant.hegde@amd.com, joerg.roedel@amd.com, tanchi25@mails.ucas.ac.cn, gong.shuai@sanechips.com.cn Cc: guoren@kernel.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org References: <20261020094106.92722-1-fangyu.yu@linux.alibaba.com> <20261020094106.92722-11-fangyu.yu@linux.alibaba.com> Content-Language: en-US From: "Nutty.Liu" In-Reply-To: <20261020094106.92722-11-fangyu.yu@linux.alibaba.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: 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wrote: > From: Fangyu Yu > > Previously, only IOTINVAL.VMA was issued, which is insufficient for > second-stage address translation consistency. > > Signed-off-by: Fangyu Yu Reviewed-by: Nutty Liu Thanks, Nutty > --- > drivers/iommu/riscv/iommu.c | 18 +++++++++++++++--- > 1 file changed, 15 insertions(+), 3 deletions(-) > > diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c > index e3791e912af3..a764a172c588 100644 > --- a/drivers/iommu/riscv/iommu.c > +++ b/drivers/iommu/riscv/iommu.c > @@ -830,6 +830,15 @@ static int riscv_iommu_iodir_set_mode(struct riscv_iommu_device *iommu, > riscv_iommu_cmd_inval_vma(&cmd); > riscv_iommu_cmd_send(iommu, &cmd); > > + /* > + * Per the RISC-V IOMMU spec (sec. 5.5), the IOMMU may retain > + * cached translations across mode switches. IOTINVAL.VMA only > + * covers first-stage leaf PTEs, so use a global IOTINVAL.GVMA > + * to flush stale second-stage translations. > + */ > + riscv_iommu_cmd_inval_gvma(&cmd); > + riscv_iommu_cmd_send(iommu, &cmd); > + > /* IOFENCE.C */ > riscv_iommu_cmd_sync(iommu, RISCV_IOMMU_IOTINVAL_TIMEOUT); > > @@ -1175,12 +1184,15 @@ static void riscv_iommu_iodir_iotinval(struct riscv_iommu_device *iommu, > /* > * else: IOTINVAL.VMA with GV=1,AV=PSCV=0,and > * GSCID=DC.iohgatp.GSCID > - * > + */ > + riscv_iommu_cmd_send(iommu, &cmd); > + /* > * IOTINVAL.GVMA with GV=1,AV=0,and > * GSCID=DC.iohgatp.GSCID > - * TODO: For now, the Second-Stage feature have not yet been merged, > - * also issue IOTINVAL.GVMA once second-stage support is merged. > */ > + riscv_iommu_cmd_inval_gvma(&cmd); > + riscv_iommu_cmd_inval_set_gscid(&cmd, > + FIELD_GET(RISCV_IOMMU_DC_IOHGATP_GSCID, iohgatp)); > } > riscv_iommu_cmd_send(iommu, &cmd); > }