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Perttunen To: Svyatoslav Ryhel , devicetree@vger.kernel.org Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jonathan Hunter , Neil Armstrong , Jessica Zhang , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Thierry Reding Subject: Re: [PATCH v6 09/10] dt-bindings: display: tegra: Document 8-bit CPU parallel interface Date: Mon, 09 Nov 2026 11:38:07 +0900 Message-ID: In-Reply-To: References: <20261105140510.165165-1-clamor95@gmail.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-ClientProxiedBy: TYCP286CA0002.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:26c::6) To SJ2PR12MB9161.namprd12.prod.outlook.com (2603:10b6:a03:566::20) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 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X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: jog4meiHHmcbY4bwwGw2V5UmJOiy7AiEaPviQdx9S9XyK3vJoogcsdPBxOpHwtzjM32S7/3Vv0cpZpk2eJKFzA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SAWPR12MB999116 On Saturday, November 7, 2026 12:51=E2=80=AFAM Thierry Reding wrote: > On Fri, Nov 06, 2026 at 04:48:17PM +0200, Svyatoslav Ryhel wrote: > > =D0=BF=D1=82, 6 =D0=BB=D0=B8=D1=81=D1=82. 2026=E2=80=AF=D1=80. =D0=BE 1= 6:40 Thierry Reding =D0=BF=D0=B8=D1=88=D0=B5: > > > > > > On Fri, Nov 06, 2026 at 04:11:12PM +0200, Svyatoslav Ryhel wrote: > > > > =D0=BF=D1=82, 6 =D0=BB=D0=B8=D1=81=D1=82. 2026=E2=80=AF=D1=80. =D0= =BE 16:08 Thierry Reding =D0=BF=D0=B8=D1=88=D0= =B5: > > > > > > > > > > On Thu, Nov 05, 2026 at 04:05:09PM +0200, Svyatoslav Ryhel wrote: > > > > > > Document 8-bit CPU parallel MIPI DBI Type B interface provided = by > > > > > > Tegra20/30 SoCs display controller. > > > > > > > > > > > > Reviewed-by: Rob Herring (Arm) > > > > > > Signed-off-by: Svyatoslav Ryhel > > > > > > --- > > > > > > .../display/tegra/nvidia,tegra20-dbi.yaml | 113 ++++++++++= ++++++++ > > > > > > .../display/tegra/nvidia,tegra20-dc.yaml | 22 ++++ > > > > > > 2 files changed, 135 insertions(+) > > > > > > create mode 100644 Documentation/devicetree/bindings/display/t= egra/nvidia,tegra20-dbi.yaml > > > > > > > > > > > [...] > > > > > > diff --git a/Documentation/devicetree/bindings/display/tegra/nv= idia,tegra20-dc.yaml b/Documentation/devicetree/bindings/display/tegra/nvid= ia,tegra20-dc.yaml > > > > > > index 69be95afd5627..ffeb124905dbf 100644 > > > > > > --- a/Documentation/devicetree/bindings/display/tegra/nvidia,te= gra20-dc.yaml > > > > > > +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,te= gra20-dc.yaml > > > > > > @@ -79,6 +79,16 @@ properties: > > > > > > rgb: > > > > > > type: object > > > > > > > > > > > > + "#address-cells": > > > > > > + const: 1 > > > > > > + > > > > > > + "#size-cells": > > > > > > + const: 0 > > > > > > + > > > > > > +patternProperties: > > > > > > + "^dbi@[0-1]$": > > > > > > + $ref: /schemas/display/tegra/nvidia,tegra20-dbi.yaml# > > > > > > > > > > I think it might be better to group these under a separate dbi no= de at > > > > > the top-level, making it a sibling to the "rgb" node. If you add > > > > > #address-cells and #size-cells here, I think that means technical= ly the > > > > > "rgb" is now in the same address space as those new dbi nodes and= would > > > > > need its own "reg" property and such. > > > > > > > > > > > > > Only 1 DBI node per DC is available. Adding address/size cells mean= s > > > > nothing for rgb. > > > > > > If only one node is available, then "reg" isn't the right property. > > > "reg" indicates we're somehow addressing the child, which applies to = all > > > children, so I don't think that would work here. A separate property > > > would make more sense in that case. > > > > >=20 > > Check v5 and talk to Mikko >=20 > I checked v5. I disagree. >=20 > Thierry My mistake; if there's only one node per DC then reg isn't the right=20 property. Mikko