From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14AD6C6379F for ; Wed, 8 Feb 2023 17:11:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231312AbjBHRLQ (ORCPT ); Wed, 8 Feb 2023 12:11:16 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42130 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230194AbjBHRLO (ORCPT ); Wed, 8 Feb 2023 12:11:14 -0500 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F146248581 for ; Wed, 8 Feb 2023 09:11:12 -0800 (PST) Received: by mail-wr1-x430.google.com with SMTP id y1so17495624wru.2 for ; Wed, 08 Feb 2023 09:11:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=7cLeU01iMrKTQSb7NiGqblMUa6KGJs2t7KVkHL7EHQk=; b=h9Xh6ZADnvzoyAa4lzuNJ3dunqiN989gqbGwMrwuADfAobTQVl8ZYv5sh4VK+jNP48 l4io5Pze8UM1YrFr2W9Cd+/5tgsPnwQor6///gucqpUtAB4CEQ1H45+pFC7O8O8NWC9U QWA09EwiCNs1El6NxGqC5tnHvfVbTUtSidx1f/wfOYib0Sqmv7MWBL8qqeFGEYPDX2Ra vu45b+L13CyUIGYQAYWef8h0zpj4qWJKkTHO+McEwWm9JXNWJ7WoiQ7IJSjiMhpbZ67I GozeHwl0TxaS61gTmWyTULXMHdGQek0xN+RfIz0BZZfyl41ywHHwgRf48J7RdJtfDkDc nlaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=7cLeU01iMrKTQSb7NiGqblMUa6KGJs2t7KVkHL7EHQk=; b=shPsNJu4eRfdRbX37FCFJVAXShW3rX3QHTZIQGYlbQH/f0dp87vcw6LlKJ/NPJiJrZ cq+R+jo5MEZSUEDBICiTsIwhrZF60HuE27udLrvr6gnNMLovq2HSOoLDswz+bwiBbNES YavkisCAmPAGF2pQo/J09p/Vao5+W96AOeDEAG8g2U5hbgfsb7Bp4MMR4yJ9VBYLnN16 1ZAayb9qReKDp4zWLP+tf4NMqqJybXvhrin/Ig79rSSEANqtc/4atiTKUHLdM2kMNG61 XLMMquJSn0W3sVIcAXfbo0GBhaGZdkmKZJT/UNOU9B6fYKRRk7miwbEzKc6mhRBAVp3F LCPg== X-Gm-Message-State: AO0yUKUN+eVhLvLFU0AmSYWCnB9oJcrS3hSwalFL4QY2/u0JXP8d/Np8 Ep3LuwEisUB56VmvFXbwLU093w== X-Google-Smtp-Source: AK7set98jhEGSGk80D+eEr7eD6Owem9Ck1coSHfJWvUYUEw5nAybGY8DOyPTrpJ/86nlYwAYwgU+gw== X-Received: by 2002:a5d:6ac5:0:b0:2c3:ea7e:be24 with SMTP id u5-20020a5d6ac5000000b002c3ea7ebe24mr7723349wrw.28.1675876271530; Wed, 08 Feb 2023 09:11:11 -0800 (PST) Received: from linaro.org ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id l11-20020a05600002ab00b002bfb5ebf8cfsm14879545wry.21.2023.02.08.09.11.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Feb 2023 09:11:10 -0800 (PST) Date: Wed, 8 Feb 2023 19:11:08 +0200 From: Abel Vesa To: Johan Hovold Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Lorenzo Pieralisi , "vkoul@kernel.org" , Kishon Vijay Abraham I , Manivannan Sadhasivam , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, Linux Kernel Mailing List Subject: Re: [PATCH v7 10/12] PCI: qcom: Add SM8550 PCIe support Message-ID: References: <20230203081807.2248625-1-abel.vesa@linaro.org> <20230203081807.2248625-11-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23-02-08 19:10:17, Abel Vesa wrote: > On 23-02-08 17:40:03, Johan Hovold wrote: > > On Mon, Feb 06, 2023 at 05:11:01PM +0200, Abel Vesa wrote: > > > On 23-02-03 10:49:24, Johan Hovold wrote: > > > > On Fri, Feb 03, 2023 at 10:18:05AM +0200, Abel Vesa wrote: > > > > > Add compatible for both PCIe found on SM8550. > > > > > Also add the cnoc_pcie_sf_axi clock needed by the SM8550. > > > > > > > > nit: You're now also adding 'noc_aggr' > > > > > > > > > Signed-off-by: Abel Vesa > > > > > Reviewed-by: Konrad Dybcio > > > > > Reviewed-by: Manivannan Sadhasivam > > > > > --- > > > > > > > @@ -182,10 +182,10 @@ struct qcom_pcie_resources_2_3_3 { > > > > > > > > > > /* 6 clocks typically, 7 for sm8250 */ > > > > > struct qcom_pcie_resources_2_7_0 { > > > > > - struct clk_bulk_data clks[12]; > > > > > + struct clk_bulk_data clks[14]; > > > > > int num_clks; > > > > > struct regulator_bulk_data supplies[2]; > > > > > - struct reset_control *pci_reset; > > > > > + struct reset_control *rst; > > > > > > > > Please name this one 'reset' or 'resets' (e.g. to avoid hard to parse > > > > things like res->rst below). > > > > > > Well, it would then be inconsitent with 2_3_3 and 2_9_0, which both use > > > rst. > > > > Yeah, I saw that. Fortunately these resources are completely > > independent, but whatever. > > Will do it in the next version then. > > > > > > > > }; > > > > > > > > > > struct qcom_pcie_resources_2_9_0 { > > > > > @@ -1177,9 +1177,9 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) > > > > > unsigned int idx; > > > > > int ret; > > > > > > > > > > - res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); > > > > > - if (IS_ERR(res->pci_reset)) > > > > > - return PTR_ERR(res->pci_reset); > > > > > + res->rst = devm_reset_control_array_get_exclusive(dev); > > > > > + if (IS_ERR(res->rst)) > > > > > + return PTR_ERR(res->rst); > > > > > > > > So the reset array implementation apparently both asserts and deasserts > > > > the resets in the order specified in DT (i.e. does not deassert in > > > > reverse order). > > > > > > > > Is that ok also for the new "pci" and "link_down" resets? > > > > > > According to the HPG, yes, this is perfectly fine. It specifically says > > > to assert the pcie reset and then continues saying to assert the > > > link_down reset. > > > > Ok, but that doesn't really say anything about whether it's ok to > > *deassert* them in the same order, which was what I asked about. > > Actually, what I wanted to say is that the HPG says something like this: > > "assert pcie reset, then assert link_down" > > and then at the end it literaly repeats the same phrase. but uses deassert instead of assert ... > > > > > > > > > Johan