From: Huang Rui <ray.huang@amd.com>
To: "Yuan, Perry" <Perry.Yuan@amd.com>
Cc: "rafael.j.wysocki@intel.com" <rafael.j.wysocki@intel.com>,
"viresh.kumar@linaro.org" <viresh.kumar@linaro.org>,
"Sharma, Deepak" <Deepak.Sharma@amd.com>,
"Limonciello, Mario" <Mario.Limonciello@amd.com>,
"Fontenot, Nathan" <Nathan.Fontenot@amd.com>,
"Deucher, Alexander" <Alexander.Deucher@amd.com>,
"Huang, Shimmer" <Shimmer.Huang@amd.com>,
"Du, Xiaojian" <Xiaojian.Du@amd.com>,
"Meng, Li (Jassmine)" <Li.Meng@amd.com>,
"linux-pm@vger.kernel.org" <linux-pm@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [RESEND PATCH V2 1/9] ACPI: CPPC: Add AMD pstate energy performance preference cppc control
Date: Mon, 17 Oct 2022 17:43:44 +0800 [thread overview]
Message-ID: <Y00j0FjodH5+yawN@amd.com> (raw)
In-Reply-To: <20221010162248.348141-2-Perry.Yuan@amd.com>
On Tue, Oct 11, 2022 at 12:22:40AM +0800, Yuan, Perry wrote:
> Add the EPP(Energy Performance Preference) support for the
> AMD SoCs without the dedicated CPPC MSR, those SoCs need to add this
> cppc acpi functions to update EPP values and desired perf value.
>
The energy performance preference register is actually defined by ACPI, so
it's not the AMD specific stuff. It's correct to define a general function
in cppc_acpi lib not only for AMD processors. We won't need to mention "AMD
P-State" energy performance preference whatever it is implemented with MSR
or SystemMemory in the subject and commit message here.
> In order to get EPP worked, cppc_get_epp_caps() will query EPP preference
> value and cppc_set_epp_perf() will set EPP new value.
> Before the EPP works, pstate driver will use cppc_set_auto_epp() to
> enable EPP function from firmware firstly.
>
> Signed-off-by: Perry Yuan <Perry.Yuan@amd.com>
> ---
> drivers/acpi/cppc_acpi.c | 128 ++++++++++++++++++++++++++++++++++++++-
> include/acpi/cppc_acpi.h | 17 ++++++
> 2 files changed, 144 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
> index 093675b1a1ff..b0e7817cb97f 100644
> --- a/drivers/acpi/cppc_acpi.c
> +++ b/drivers/acpi/cppc_acpi.c
> @@ -1365,6 +1365,132 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs)
> }
> EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs);
>
> +/**
> + * cppc_get_epp_caps - Get the energy preference register value.
> + * @cpunum: CPU from which to get epp preference level.
> + * @perf_caps: Return address.
> + *
> + * Return: 0 for success, -EIO otherwise.
> + */
> +int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps)
> +{
> + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum);
> + struct cpc_register_resource *energy_perf_reg;
> + u64 energy_perf;
> +
> + if (!cpc_desc) {
> + pr_warn("No CPC descriptor for CPU:%d\n", cpunum);
> + return -ENODEV;
> + }
> +
> + energy_perf_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
> +
> + if (!CPC_SUPPORTED(energy_perf_reg))
> + pr_warn("energy perf reg update is unsupported!\n");
> +
> + if (CPC_IN_PCC(energy_perf_reg)) {
> + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum);
> + struct cppc_pcc_data *pcc_ss_data = NULL;
> + int ret = 0;
> +
> + if (pcc_ss_id < 0)
> + return -EIO;
Should be -ENODEV. That means no subspace.
> +
> + pcc_ss_data = pcc_data[pcc_ss_id];
> +
> + down_write(&pcc_ss_data->pcc_lock);
> +
> + if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) {
> + cpc_read(cpunum, energy_perf_reg, &energy_perf);
> + perf_caps->energy_perf = energy_perf;
> + } else {
> + ret = -EIO;
> + }
> +
> + up_write(&pcc_ss_data->pcc_lock);
> +
> + return ret;
> + }
> +
> + return 0;
> +}
> +EXPORT_SYMBOL_GPL(cppc_get_epp_caps);
> +
> +int cppc_set_auto_epp(int cpu, bool enable)
> +{
> + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
> + struct cpc_register_resource *auto_sel_reg;
> + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
> + struct cppc_pcc_data *pcc_ss_data = NULL;
> + int ret = -EINVAL;
> +
> + if (!cpc_desc) {
> + pr_warn("No CPC descriptor for CPU:%d\n", cpu);
> + return -EINVAL;
> + }
> +
> + auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE];
> +
> + if (CPC_IN_PCC(auto_sel_reg)) {
> + if (pcc_ss_id < 0)
> + return -EIO;
The same comment with above, should be -ENODEV.
> +
> + ret = cpc_write(cpu, auto_sel_reg, enable);
> + if (ret)
> + return ret;
> +
> + pcc_ss_data = pcc_data[pcc_ss_id];
> +
> + down_write(&pcc_ss_data->pcc_lock);
> + /* after writing CPC, transfer the ownership of PCC to platform */
> + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
> + up_write(&pcc_ss_data->pcc_lock);
> + return ret;
> + }
> +
> + return cpc_write(cpu, auto_sel_reg, enable);
> +}
> +EXPORT_SYMBOL_GPL(cppc_set_auto_epp);
> +
> +/*
> + * Set Energy Performance Preference Register value through
> + * Performance Controls Interface
> + */
> +int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
> +{
> + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu);
> + struct cpc_register_resource *epp_set_reg;
> + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu);
> + struct cppc_pcc_data *pcc_ss_data = NULL;
> + int ret = -EINVAL;
> +
> + if (!cpc_desc) {
> + pr_warn("No CPC descriptor for CPU:%d\n", cpu);
> + return -EINVAL;
> + }
> +
> + epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF];
> +
> + if (CPC_IN_PCC(epp_set_reg)) {
> + if (pcc_ss_id < 0)
> + return -EIO;
The same comment with above, should be -ENODEV.
> +
> + ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf);
> + if (ret)
> + return ret;
> +
> + pcc_ss_data = pcc_data[pcc_ss_id];
> +
> + down_write(&pcc_ss_data->pcc_lock);
> + /* after writing CPC, transfer the ownership of PCC to platform */
> + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
> + up_write(&pcc_ss_data->pcc_lock);
> + }
> +
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(cppc_set_epp_perf);
> +
Most of cppc_set_auto_epp and cppc_set_epp_perf implementations are
duplicated. Could you use one general function?
> /**
> * cppc_set_enable - Set to enable CPPC on the processor by writing the
> * Continuous Performance Control package EnableRegister field.
> @@ -1400,7 +1526,7 @@ int cppc_set_enable(int cpu, bool enable)
> pcc_ss_data = pcc_data[pcc_ss_id];
>
> down_write(&pcc_ss_data->pcc_lock);
> - /* after writing CPC, transfer the ownership of PCC to platfrom */
> + /* after writing CPC, transfer the ownership of PCC to platform */
There is no change with this line.
Thanks,
Ray
> ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE);
> up_write(&pcc_ss_data->pcc_lock);
> return ret;
> diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h
> index c5614444031f..10d91aeedaca 100644
> --- a/include/acpi/cppc_acpi.h
> +++ b/include/acpi/cppc_acpi.h
> @@ -108,12 +108,14 @@ struct cppc_perf_caps {
> u32 lowest_nonlinear_perf;
> u32 lowest_freq;
> u32 nominal_freq;
> + u32 energy_perf;
> };
>
> struct cppc_perf_ctrls {
> u32 max_perf;
> u32 min_perf;
> u32 desired_perf;
> + u32 energy_perf;
> };
>
> struct cppc_perf_fb_ctrs {
> @@ -149,6 +151,9 @@ extern bool cpc_ffh_supported(void);
> extern bool cpc_supported_by_cpu(void);
> extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val);
> extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val);
> +extern int cppc_set_auto_epp(int cpu, bool enable);
> +extern int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps);
> +extern int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls);
> #else /* !CONFIG_ACPI_CPPC_LIB */
> static inline int cppc_get_desired_perf(int cpunum, u64 *desired_perf)
> {
> @@ -202,6 +207,18 @@ static inline int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
> {
> return -ENOTSUPP;
> }
> +static inline int cppc_set_auto_epp(int cpu, bool enable)
> +{
> + return -ENOTSUPP;
> +}
> +static inline int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls)
> +{
> + return -ENOTSUPP;
> +}
> +static inline int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps)
> +{
> + return -ENOTSUPP;
> +}
> #endif /* !CONFIG_ACPI_CPPC_LIB */
>
> #endif /* _CPPC_ACPI_H*/
> --
> 2.34.1
>
next prev parent reply other threads:[~2022-10-17 9:44 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-10 16:22 [RESEND PATCH V2 0/9] Implement AMD Pstate EPP Driver Perry Yuan
2022-10-10 16:22 ` [RESEND PATCH V2 1/9] ACPI: CPPC: Add AMD pstate energy performance preference cppc control Perry Yuan
2022-10-17 9:43 ` Huang Rui [this message]
2022-10-10 16:22 ` [RESEND PATCH V2 2/9] cpufreq: amd_pstate: add module parameter to load amd pstate EPP driver Perry Yuan
2022-10-17 9:47 ` Huang Rui
2022-10-20 15:56 ` Yuan, Perry
2022-10-10 16:22 ` [RESEND PATCH V2 3/9] cpufreq: cpufreq: export cpufreq cpu release and acquire Perry Yuan
2022-10-10 16:22 ` [RESEND PATCH V2 4/9] x86/msr: Add the MSR definition for AMD CPPC boost state Perry Yuan
2022-10-17 9:56 ` Huang Rui
2022-10-20 16:01 ` Yuan, Perry
2022-10-20 16:05 ` Limonciello, Mario
2022-10-20 16:08 ` Yuan, Perry
2022-10-21 5:22 ` Huang Rui
2022-10-21 9:37 ` Borislav Petkov
2022-10-24 2:58 ` Yuan, Perry
2022-10-24 2:56 ` Yuan, Perry
2022-10-25 0:32 ` Huang Rui
2022-10-25 13:23 ` Yuan, Perry
2022-10-10 16:22 ` [RESEND PATCH V2 5/9] Documentation: amd-pstate: add EPP profiles introduction Perry Yuan
2022-10-10 16:22 ` [RESEND PATCH V2 6/9] cpufreq: amd_pstate: add AMD pstate EPP support for shared memory type processor Perry Yuan
2022-10-17 10:54 ` Huang Rui
2022-10-20 16:04 ` Yuan, Perry
2022-10-25 0:25 ` Huang Rui
2022-10-10 16:22 ` [RESEND PATCH V2 7/9] cpufreq: amd_pstate: add AMD Pstate EPP support for the MSR based processors Perry Yuan
2022-10-11 2:54 ` Viresh Kumar
2022-10-11 5:45 ` Yuan, Perry
2022-10-17 11:17 ` Huang Rui
2022-10-10 16:22 ` [RESEND PATCH V2 8/9] cpufreq: amd_pstate: implement amd pstate cpu online and offline callback Perry Yuan
2022-10-10 16:22 ` [RESEND PATCH V2 9/9] cpufreq: amd-pstate: implement suspend and resume callbacks Perry Yuan
2022-10-12 12:06 ` [RESEND PATCH V2 0/9] Implement AMD Pstate EPP Driver Russell Haley
2022-10-17 7:40 ` Huang Rui
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