From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C8880C4332F for ; Tue, 18 Oct 2022 09:40:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229967AbiJRJka (ORCPT ); Tue, 18 Oct 2022 05:40:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46116 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229718AbiJRJk1 (ORCPT ); Tue, 18 Oct 2022 05:40:27 -0400 Received: from casper.infradead.org (casper.infradead.org [IPv6:2001:8b0:10b:1236::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7DA689E2C3 for ; Tue, 18 Oct 2022 02:40:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=+oHCmlSrQtOe8KtXGCGb0Hin+gSSgOm6PLxBdj0ubKs=; b=Y+ZmAXaWxb7eioaQCzFdKi4Yvw 8D1TQ1fu8m2Uc0N9P2PNrei7toGIWqnw6Q8sVeBaWs7f3ympxkJWLP28TNbTlAshM190Jsz9sPZ+j wvQNvy8B4XJD5w1NUl4afrqcQ2k1RHECOVjuaH2Ac76siUv8stzUqu5g50pumWffVT4ewmsfddMYL hfffRoUAYs9rVqbrwISxVU5tnNiDYKzvPKlMBOeTjHl8ogWV3/yPn2FwL77m5P0RBP/aD1j257l4b vbaM4AALzT20cAMJrAZy89fLpamOCh5euDPqaxpgcd/+vHuTayD10IEo+pD30jAizoASqvHW7kgIY o71RJPnQ==; Received: from j130084.upc-j.chello.nl ([24.132.130.84] helo=noisy.programming.kicks-ass.net) by casper.infradead.org with esmtpsa (Exim 4.94.2 #2 (Red Hat Linux)) id 1okj56-00AdTz-G0; Tue, 18 Oct 2022 09:40:16 +0000 Received: from hirez.programming.kicks-ass.net (hirez.programming.kicks-ass.net [192.168.1.225]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (Client did not present a certificate) by noisy.programming.kicks-ass.net (Postfix) with ESMTPS id 663AD30004F; Tue, 18 Oct 2022 11:40:11 +0200 (CEST) Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id 47A692C3855A4; Tue, 18 Oct 2022 11:40:11 +0200 (CEST) Date: Tue, 18 Oct 2022 11:40:11 +0200 From: Peter Zijlstra To: Ricardo Neri Cc: Juri Lelli , Vincent Guittot , Ricardo Neri , "Ravi V. Shankar" , Ben Segall , Daniel Bristot de Oliveira , Dietmar Eggemann , Len Brown , Mel Gorman , "Rafael J. Wysocki" , Srinivas Pandruvada , Steven Rostedt , Tim Chen , Valentin Schneider , x86@kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 0/4] sched/fair: Avoid unnecessary migrations within SMT domains Message-ID: References: <20220825225529.26465-1-ricardo.neri-calderon@linux.intel.com> <20221018023527.GB23064@ranerica-svr.sc.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221018023527.GB23064@ranerica-svr.sc.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Oct 17, 2022 at 07:35:27PM -0700, Ricardo Neri wrote: > On Thu, Aug 25, 2022 at 03:55:25PM -0700, Ricardo Neri wrote: > > Intel processors that support Intel Turbo Boost Max 3.0 use asym_packing > > to assign higher priorities to CPUs with higher maximum frequencies. It > > artificially assigns, however, a lower priority to the higher-numbered > > SMT siblings to ensure that they are used last. > > > > This results in unnecessary task migrations within the SMT domains. > > > > On processors with a mixture of higher-frequency SMT cores and lower- > > frequency non-SMT cores (such as Intel hybrid processors), a lower- > > priority CPU pulls tasks from the higher-priority cores if more than one > > SMT sibling is busy. > > > > Do not use different priorities for each SMT sibling. Instead, tweak the > > asym_packing load balancer to recognize SMT cores with more than one > > busy sibling and let lower-priority CPUs pull tasks. > > > > Removing these artificial priorities avoids superfluous migrations and > > lets lower-priority cores inspect all SMT siblings for the busiest queue. > > Hello. I'd like to know if there are any comments on these patches. This > patchset is a requisite for the IPC classes of tasks patchset [1]. Urgh.. so I'm not liking this, afaict you're sprinkling SMT2 assumptions. Why can't we make arch_asym_cpu_priority() depend on CPU state? Doesn't it then magically work?