From: Christoph Hellwig <hch@infradead.org>
To: Rui Ma <Rui.Ma@amd.com>
Cc: helgaas@kernel.org, linux-kernel@vger.kernel.org,
linux-pci@vger.kernel.org, Alexander.Deucher@amd.com,
bhelgaas@google.com
Subject: Re: [PATCH] PCI/IOV: Decrease VF memory BAR size to save host memory occupied by PTEs
Date: Sun, 16 Oct 2022 23:26:48 -0700 [thread overview]
Message-ID: <Y0z1qIG3i3+CZRiX@infradead.org> (raw)
In-Reply-To: <20221011112325.992317-1-Rui.Ma@amd.com>
Besides the various style issues: I don't think we can just
hardcode specific devices in the PCIe core. If we want to do this
we'll need something like PCIe extended capabilities or ACPI tables
to describe the behavior in a standardized way.
next prev parent reply other threads:[~2022-10-17 6:26 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-11 11:23 Rui Ma
2022-10-11 11:37 ` Leon Romanovsky
2022-10-11 11:48 ` David Laight
2022-10-17 6:26 ` Christoph Hellwig [this message]
2022-11-09 23:46 ` Bjorn Helgaas
-- strict thread matches above, loose matches on Subject: below --
2022-09-26 8:05 Rui Ma
2022-09-27 22:06 ` Bjorn Helgaas
2022-10-11 11:19 ` Ma, Rui
2022-10-11 14:05 ` Deucher, Alexander
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