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From: Andrew Lunn <andrew@lunn.ch>
To: Chester Lin <clin@suse.com>
Cc: "Giuseppe Cavallaro" <peppe.cavallaro@st.com>,
	"Alexandre Torgue" <alexandre.torgue@foss.st.com>,
	"Jose Abreu" <joabreu@synopsys.com>,
	netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	"David S. Miller" <davem@davemloft.net>,
	"Eric Dumazet" <edumazet@google.com>,
	"Jakub Kicinski" <kuba@kernel.org>,
	"Paolo Abeni" <pabeni@redhat.com>,
	"Jan Petrous" <jan.petrous@nxp.com>,
	"Ondrej Spacek" <ondrej.spacek@nxp.com>,
	"Ghennadi Procopciuc" <Ghennadi.Procopciuc@nxp.com>,
	"Andra-Teodora Ilie" <andra.ilie@nxp.com>,
	"Andreas Färber" <afaerber@suse.de>,
	"Matthias Brugger" <mbrugger@suse.com>
Subject: Re: [PATCH 5/5] net: stmmac: Add NXP S32 SoC family support
Date: Mon, 31 Oct 2022 14:27:17 +0100	[thread overview]
Message-ID: <Y1/NNbZiVvM9+mrm@lunn.ch> (raw)
In-Reply-To: <20221031101052.14956-6-clin@suse.com>

> +	/* set interface mode */
> +	if (gmac->ctrl_sts) {
> +		switch (gmac->intf_mode) {
> +		default:
> +			dev_info(&pdev->dev, "unsupported mode %u, set the default phy mode.\n",
> +				 gmac->intf_mode);

If it is an unsupported mode use dev_err() and return -EINVAL;

> +			fallthrough;
> +		case PHY_INTERFACE_MODE_SGMII:
> +			dev_info(&pdev->dev, "phy mode set to SGMII\n");

dev_dbg()

Please don't spam the lock with useless information.

> +			intf_sel = PHY_INTF_SEL_SGMII;
> +			break;
> +		case PHY_INTERFACE_MODE_RGMII:
> +		case PHY_INTERFACE_MODE_RGMII_ID:
> +		case PHY_INTERFACE_MODE_RGMII_TXID:
> +		case PHY_INTERFACE_MODE_RGMII_RXID:
> +			dev_info(&pdev->dev, "phy mode set to RGMII\n");

dev_dbg()

> +			intf_sel = PHY_INTF_SEL_RGMII;
> +			break;
> +		case PHY_INTERFACE_MODE_RMII:
> +			dev_info(&pdev->dev, "phy mode set to RMII\n");

dev_dbg()

> +			intf_sel = PHY_INTF_SEL_RMII;
> +			break;
> +		case PHY_INTERFACE_MODE_MII:
> +			dev_info(&pdev->dev, "phy mode set to MII\n");

dev_dbg()

> +			intf_sel = PHY_INTF_SEL_MII;
> +			break;
> +		}
> +
> +		writel(intf_sel, gmac->ctrl_sts);
> +	}
> +
> +	return 0;
> +}
> +
> +static int s32cc_config_cache_coherency(struct platform_device *pdev,
> +					struct plat_stmmacenet_data *plat_dat)
> +{
> +	plat_dat->axi4_ace_ctrl =
> +		devm_kzalloc(&pdev->dev,
> +			     sizeof(struct stmmac_axi4_ace_ctrl),
> +			     GFP_KERNEL);
> +
> +	if (!plat_dat->axi4_ace_ctrl) {
> +		dev_info(&pdev->dev, "Fail to allocate axi4_ace_ctrl\n");

dev_err(). But devm_kzalloc() failing will produce log messages, so
you probably don't need this.

    Andrew

      reply	other threads:[~2022-10-31 13:27 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-31 10:10 [PATCH 0/5] Add GMAC support for S32 SoC family Chester Lin
2022-10-31 10:10 ` [PATCH 1/5] dt-bindings: net: snps, dwmac: add NXP S32CC support Chester Lin
2022-10-31 10:10 ` [PATCH 2/5] dt-bindings: net: add schema for NXP S32CC dwmac glue driver Chester Lin
2022-11-02 15:55   ` Rob Herring
2022-11-02 17:13     ` Andreas Färber
2022-11-02 21:44       ` Rob Herring
2022-11-04 10:11         ` Chester Lin
2022-11-03 22:05       ` Andrew Lunn
2022-11-04 11:39         ` Chester Lin
2022-11-04 13:30           ` Andrew Lunn
2022-11-09  8:09             ` Chester Lin
2022-11-09 22:55           ` [EXT] " Jan Petrous
2022-11-09 23:00             ` Andrew Lunn
2022-11-10  8:51               ` Jan Petrous
2022-11-10 13:04                 ` Andrew Lunn
2022-11-09 22:55       ` Jan Petrous
2022-10-31 10:10 ` [PATCH 3/5] net: stmmac: Add CSR clock 500Mhz/800Mhz support Chester Lin
2022-10-31 10:10 ` [PATCH 4/5] net: stmmac: Add AXI4 ACE control support Chester Lin
2022-10-31 10:10 ` [PATCH 5/5] net: stmmac: Add NXP S32 SoC family support Chester Lin
2022-10-31 13:27   ` Andrew Lunn [this message]

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