From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA029C433FE for ; Thu, 20 Oct 2022 13:49:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229738AbiJTNt0 (ORCPT ); Thu, 20 Oct 2022 09:49:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229746AbiJTNsy (ORCPT ); Thu, 20 Oct 2022 09:48:54 -0400 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 090C55B9CA for ; Thu, 20 Oct 2022 06:48:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1666273734; x=1697809734; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=DFlm0KbEbGovx+beuTWPd+BvaHeRPvibkM66WhpiDVg=; b=hzccy7yx9M2GoA/wDDb8BTZawXgFkbjAMJZTQxtjB8YLnNJXt4P4NHGl ez53LXlAqHeI856eOXPs8baG/LwM0eO4AH/aYmMisH2OLRjZd4D1L5TK3 vl6FH32SIFfNoG8NY4svMmd9i8fvdwu30OSiCpKGZhpXXS7nkmBnLLHpk iKomBaQP+Pa/BcWz8WFpaeXnSQPDRxDTGwiY7aA27kJFGaPh8ABcgXUsC qKfwkXNzA47gdx1B7kNCpycKuTD1v2Zyop8Bo27e+r9InlT0TpjXSv/o4 FFeWGcNzr4uN8i1zLoEA/526TprDcPObmgXAp+FCqnVq1ZXf2Jawq1wOO w==; X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="294105178" X-IronPort-AV: E=Sophos;i="5.95,198,1661842800"; d="scan'208";a="294105178" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Oct 2022 06:48:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10506"; a="734847691" X-IronPort-AV: E=Sophos;i="5.95,198,1661842800"; d="scan'208";a="734847691" Received: from smile.fi.intel.com ([10.237.72.54]) by fmsmga002.fm.intel.com with ESMTP; 20 Oct 2022 06:48:51 -0700 Received: from andy by smile.fi.intel.com with local (Exim 4.96) (envelope-from ) id 1olVuj-00AZSH-2R; Thu, 20 Oct 2022 16:48:49 +0300 Date: Thu, 20 Oct 2022 16:48:49 +0300 From: Andy Shevchenko To: Randy Dunlap Cc: Hans de Goede , Linus Torvalds , Lee Jones , Mark Brown , Linux Kernel Mailing List Subject: Re: [GIT PULL] Backlight for v6.1 Message-ID: References: <189ed242-4ccb-4935-ede0-c5807d7b5083@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Oct 19, 2022 at 08:31:33PM -0700, Randy Dunlap wrote: > On 10/9/22 05:58, Hans de Goede wrote: > > On 10/9/22 01:23, Linus Torvalds wrote: > >> On Sat, Oct 8, 2022 at 12:59 PM Hans de Goede wrote: ... > >> Because if it depends on some symbols from I2C_DESIGNWARE_PLATFORM, > >> and that one can be a module, then the Intel PMIC driver also needs to > >> be built as a module to just get the build coverage, at least. > > I don't see intel_soc_pmic_crc.c using any direct calls into > i2c-designware-platform code. If it calls into it, it must be thru some > indirect pointers (?). It's on hardware level, the PMIC is connected to the I²C host controller, which is Synopsys DesignWare and being services by the respective driver. Any access to the PMIC's registers requires the I²C to be involved. What we talked above is even bigger loop, that takes AML code in the chain. -- With Best Regards, Andy Shevchenko