From: Peter Zijlstra <peterz@infradead.org>
To: Linus Torvalds <torvalds@linux-foundation.org>
Cc: x86@kernel.org, dave.hansen@intel.com,
linux-kernel@vger.kernel.org, oliver.sang@intel.com
Subject: Re: [PATCH 1/4] x86/mm: Add a few comments
Date: Thu, 10 Nov 2022 19:02:31 +0100 [thread overview]
Message-ID: <Y208t7Lw9n+3CNz3@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <CAHk-=wg8UrshBBLioF0+FaJvAkSTRkH3-aqKT3eAWHtBp57hxw@mail.gmail.com>
On Thu, Nov 10, 2022 at 08:22:54AM -0800, Linus Torvalds wrote:
> On Thu, Nov 10, 2022 at 4:58 AM Peter Zijlstra <peterz@infradead.org> wrote:
> >
> > It's a shame to hide useful comments in Changelogs, add some to the
> > code.
> >
> > Shamelessly stolen from commit:
>
> When the comment says how the image is mapped into two places,
> wouldn't it be good to also have the reason *why* rather than just
> what..
Agreed, and I think I can actually answer this. How about I change it
into something like this:
/*
* The kernel image is mapped into two places in the virtual address space
* (addresses without KASLR, of course):
*
* 1. The kernel direct map (0xffff880000000000)
* 2. The "high kernel map" (0xffffffff81000000)
*
* We actually execute out of #2. If we get the address of a kernel symbol, it
* points to #2, but almost all physical-to-virtual translations point to #1.
*
* This is so that we can have both a directmap of all physical memory
* *and* take full advantage of the limited (s32) immediate addressing
* range (2G) of x86_64.
*
* See Documentation/x86/x86_64/mm.rst for more details.
*/
> That said, my real commentary for this patch set is not that
> particular instance, but the bigger picture - that this code is still
> a bit opaque as to why these things are done.
Yes, small steps I suppose. It took me way longer than it should have to
figure out what this code was actually doing. And why we shouldn't
propagate those NX bits in the various cases.
> Do we need any of those alias passes at all for pure protection bit
> changes? I thought we only did these because things like cacheability
> bits have to be in sync due to machine checks etc?
>
> Or am I missing some case where writability matters too?
I _think_, but I'm not actually sure, that it matters in exactly that
case dhansen mentions, where we do a physical to virtual address
translation and expect access to match whatever alias we originally came
from.
next prev parent reply other threads:[~2022-11-10 18:03 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-10 12:52 [PATCH 0/4] x86/mm: Fix set_memory_rox() Peter Zijlstra
2022-11-10 12:52 ` [PATCH 1/4] x86/mm: Add a few comments Peter Zijlstra
2022-11-10 16:22 ` Linus Torvalds
2022-11-10 18:02 ` Peter Zijlstra [this message]
2022-11-11 11:50 ` Peter Zijlstra
2022-11-10 12:52 ` [PATCH 2/4] x86/mm: Untangle __change_page_attr_set_clr(.checkalias) Peter Zijlstra
2022-11-10 12:52 ` [PATCH 3/4] x86/mm: Inhibit _PAGE_NX changes from cpa_process_alias() Peter Zijlstra
2022-11-14 16:08 ` Dave Hansen
2022-11-10 12:52 ` [PATCH 4/4] x86/mm: Rename __change_page_attr_set_clr(.checkalias) Peter Zijlstra
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