Re: [PATCH] drm/bridge: ti-sn65dsi86: Fix output polarity setting bug

[Laurent Pinchart <laurent.pinchart@ideasonboard.com>]

Adding Tomi to the CC list. Tomi, would you be able to test this ?

On Fri, Nov 25, 2022 at 06:45:58PM +0800, Qiqi Zhang wrote:
> According to the description in ti-sn65dsi86's datasheet:
> 
> CHA_HSYNC_POLARITY:
> 0 = Active High Pulse. Synchronization signal is high for the sync
> pulse width. (default)
> 1 = Active Low Pulse. Synchronization signal is low for the sync
> pulse width.
> 
> CHA_VSYNC_POLARITY:
> 0 = Active High Pulse. Synchronization signal is high for the sync
> pulse width. (Default)
> 1 = Active Low Pulse. Synchronization signal is low for the sync
> pulse width.
> 
> We should only set these bits when the polarity is negative.
> Signed-off-by: Qiqi Zhang <eddy.zhang@rock-chips.com>
> ---
>  drivers/gpu/drm/bridge/ti-sn65dsi86.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> index 3c3561942eb6..eb24322df721 100644
> --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c
> @@ -931,9 +931,9 @@ static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata)
>  		&pdata->bridge.encoder->crtc->state->adjusted_mode;
>  	u8 hsync_polarity = 0, vsync_polarity = 0;
>  
> -	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
> +	if (mode->flags & DRM_MODE_FLAG_NHSYNC)
>  		hsync_polarity = CHA_HSYNC_POLARITY;
> -	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
> +	if (mode->flags & DRM_MODE_FLAG_NVSYNC)
>  		vsync_polarity = CHA_VSYNC_POLARITY;
>  
>  	ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,

-- 
Regards,

Laurent Pinchart