On Wed, Dec 07, 2022 at 06:27:52PM +0000, Russell King (Oracle) wrote:
> On Wed, Dec 07, 2022 at 05:44:58PM +0100, Jonathan Neuschäfer wrote:
> > On Wed, Dec 07, 2022 at 03:41:11PM +0000, Russell King (Oracle) wrote:
> > > On Wed, Dec 07, 2022 at 04:28:07PM +0100, Andrew Lunn wrote:
> > [...]
> > > > How are the registers arranged?
> > > 
> > > As documented in drivers/gpio/gpio-pxa.c - it'll be easier for you to
> > > look there rather than for me to explain it - but suffice it to say
> > > that the pinctrl registers are amongst the GPIO registers.
> > > 
> > > > Is 0x40e00000-0x40e0ffff simply too
> > > > large, and making it smaller would fix the issue? Or are the registers
> > > > interleaved?
> > > 
> > > They're interleaved. Looking at the .dtsi file for PXA25x, it seems
> > > that the pinctrl claims just the addresses that it needs, but the GPIO
> > > controller has no reg property in the .dtsi, so I'm not sure what fills
> > > that information in.
> > 
> > The GPIO reg property is in pxa2xx.dtsi.
> 
> Looks to me like pxa25x should override the reg property with a smaller
> range (0x54) and  pxa27x probably should have used a second set of
> entries in reg the subsequent group of 3 gpio blocks at offset 0x100.

Without further code changes this wouldn't be sufficient, because the
pinctrl driver also touches the GPIO direction registers at offset
0x0c-0x14.


Jonathan