From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05EB4C4332F for ; Tue, 13 Dec 2022 05:54:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234269AbiLMFx6 (ORCPT ); Tue, 13 Dec 2022 00:53:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233843AbiLMFxz (ORCPT ); Tue, 13 Dec 2022 00:53:55 -0500 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15B7F1A388; Mon, 12 Dec 2022 21:53:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1670910835; x=1702446835; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=O0o4lAUzDqGUs/CLDXsUApPxOyhZc014w9/u54eWA28=; b=MVWSV7DG6lml2aSomrpqcsph/vhy7gtYOu1Kl8n74hMqSfTswYeZejSC m2/VR3F5PHFXdA/vigMNPNb0HS1a2FS54WvPRyEnzc5QKHBfKRgFZ1po7 hnCjjOOpqkGmf4nUAxxtFZesigWmKNzeM6ygIAik7aucTUQV6yn9/342w DhIHXJMnC+bSy/rYhZPRBS56F9KyS8H423WOiXhFWBXk+kjfX7uVhSKdd agHidKYiVhIC3rLvVaN1WkuCs/VOwsy1Ntb6v0xic1lnFvKtgIGIwFbAk 3y3vrAUtsUXl5RW12I3CbCnyC+MrJOs2pSm6juk3ODdcFYCDaMHrlZEL+ g==; X-IronPort-AV: E=McAfee;i="6500,9779,10559"; a="316752061" X-IronPort-AV: E=Sophos;i="5.96,240,1665471600"; d="scan'208";a="316752061" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Dec 2022 21:53:54 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6500,9779,10559"; a="977328613" X-IronPort-AV: E=Sophos;i="5.96,240,1665471600"; d="scan'208";a="977328613" Received: from yilunxu-optiplex-7050.sh.intel.com (HELO localhost) ([10.239.159.165]) by fmsmga005.fm.intel.com with ESMTP; 12 Dec 2022 21:53:52 -0800 Date: Tue, 13 Dec 2022 13:44:00 +0800 From: Xu Yilun To: Ilpo =?iso-8859-1?Q?J=E4rvinen?= Cc: linux-fpga@vger.kernel.org, Wu Hao , Tom Rix , Moritz Fischer , Lee Jones , Matthew Gerlach , Russ Weight , Tianfei zhang , Mark Brown , Greg KH , Marco Pagani , linux-kernel@vger.kernel.org Subject: Re: [PATCH v4 5/8] fpga: intel-m10-bmc: Rework flash read/write Message-ID: References: <20221211103913.5287-1-ilpo.jarvinen@linux.intel.com> <20221211103913.5287-6-ilpo.jarvinen@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20221211103913.5287-6-ilpo.jarvinen@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 2022-12-11 at 12:39:10 +0200, Ilpo Järvinen wrote: > Access to flash staging area is different for N6000 from that of the > SPI interfaced counterparts. To make it easier to differentiate flash > access path, move read/write into new functions where the new access > path can be easily placed into. Rework the unaligned access such the > behavior it matches for both read and write. > > This change also renames m10bmc_sec_write() to m10bmc_sec_fw_write() as > it would have a name conflict otherwise. > > Co-developed-by: Tianfei zhang > Signed-off-by: Tianfei zhang > Co-developed-by: Russ Weight > Signed-off-by: Russ Weight > Signed-off-by: Ilpo Järvinen Acked-by: Xu Yilun