On Tue, Jan 03, 2023 at 07:44:49AM +0100, Björn Töpel wrote: > Conor Dooley writes: > > On Mon, Jan 02, 2023 at 05:07:48PM +0100, Björn Töpel wrote: > >> From: Björn Töpel > >> diff --git a/arch/riscv/kernel/probes/simulate-insn.h b/arch/riscv/kernel/probes/simulate-insn.h > >> index cb6ff7dccb92..de8474146a9b 100644 > >> --- a/arch/riscv/kernel/probes/simulate-insn.h > >> +++ b/arch/riscv/kernel/probes/simulate-insn.h > >> @@ -31,9 +31,9 @@ __RISCV_INSN_FUNCS(fence, 0x7f, 0x0f); > >> } while (0) > >> > >> __RISCV_INSN_FUNCS(c_j, 0xe003, 0xa001); > >> -__RISCV_INSN_FUNCS(c_jr, 0xf007, 0x8002); > > > > Hmm, I wonder where the mask originally came from! > > I think it's just a simple bug -- missing that "rs2" must be zero. > > > I had a look at the compressed spec, of which the version google gave to > > me was v1.9 [1], and Table 1.6 in that (Instruction listing for RVC, > > Quadrant 2) seems to list them all together. > > [1] - > > https://riscv.org/wp-content/uploads/2015/11/riscv-compressed-spec-v1.9.pdf > > C-ext is part of the unpriv spec: > https://github.com/riscv/riscv-isa-manual/releases Yah, I was trying to see if there was some period piece which was misleading that would have explained the mask. I looked again & the v1.7 spec doesn't have that table, but also has no reason to suggest the current mask either. Guess it was just a mistake :)