From: Mark Brown <broonie@kernel.org>
To: Rob Herring <robh@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>,
Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Marc Zyngier <maz@kernel.org>, James Morse <james.morse@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Namhyung Kim <namhyung@kernel.org>,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev,
linux-perf-users@vger.kernel.org,
James Clark <james.clark@arm.com>
Subject: Re: [PATCH v4 3/8] arm64/sysreg: Convert SPE registers to automatic generation
Date: Mon, 9 Jan 2023 19:33:33 +0000 [thread overview]
Message-ID: <Y7xsDXFlNjiQ1AIe@sirena.org.uk> (raw)
In-Reply-To: <20220825-arm-spe-v8-7-v4-3-327f860daf28@kernel.org>
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On Mon, Jan 09, 2023 at 01:26:19PM -0600, Rob Herring wrote:
> Convert all the SPE register defines to automatic generation. No
> functional changes.
>
> New registers and fields for SPEv1.2 are added with the conversion.
>
> Some of the PMBSR MSS field defines are kept as the automatic generation
> has no way to create multiple names for the same register bits. The
> meaning of the MSS field depends on other bits.
>
> Tested-by: James Clark <james.clark@arm.com>
> Signed-off-by: Rob Herring <robh@kernel.org>
> ---
> v4:
> - Rebase on v6.2-rc1
> v3:
> - Make some fields enums and add some missing fields
What changed to invalidate my Reviewed-by?
https://lore.kernel.org/all/Y2kgC9QlBwvXTLe6@sirena.org.uk/
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next prev parent reply other threads:[~2023-01-09 19:33 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-09 19:26 [PATCH v4 0/8] perf: Arm SPEv1.2 support Rob Herring
2023-01-09 19:26 ` [PATCH v4 1/8] perf: arm_spe: Use feature numbering for PMSEVFR_EL1 defines Rob Herring
2023-01-10 6:48 ` Anshuman Khandual
2023-01-09 19:26 ` [PATCH v4 2/8] arm64: Drop SYS_ from SPE register defines Rob Herring
2023-01-10 7:54 ` Anshuman Khandual
2023-01-09 19:26 ` [PATCH v4 3/8] arm64/sysreg: Convert SPE registers to automatic generation Rob Herring
2023-01-09 19:33 ` Mark Brown [this message]
2023-01-09 20:18 ` Rob Herring
2023-01-09 20:40 ` Mark Brown
2023-01-10 8:05 ` Anshuman Khandual
2023-01-09 19:26 ` [PATCH v4 4/8] perf: arm_spe: Drop BIT() and use FIELD_GET/PREP accessors Rob Herring
2023-01-10 8:36 ` Anshuman Khandual
2023-01-09 19:26 ` [PATCH v4 5/8] perf: arm_spe: Use new PMSIDR_EL1 register enums Rob Herring
2023-01-10 8:46 ` Anshuman Khandual
2023-01-09 19:26 ` [PATCH v4 6/8] perf: arm_spe: Support new SPEv1.2/v8.7 'not taken' event Rob Herring
2023-01-10 8:54 ` Anshuman Khandual
2023-01-09 19:26 ` [PATCH v4 7/8] perf: Add perf_event_attr::config3 Rob Herring
2023-02-04 10:36 ` Peter Zijlstra
2023-01-09 19:26 ` [PATCH v4 8/8] perf: arm_spe: Add support for SPEv1.2 inverted event filtering Rob Herring
2023-01-19 19:08 ` [PATCH v4 0/8] perf: Arm SPEv1.2 support Will Deacon
2023-02-07 12:39 ` Will Deacon
2023-02-07 12:42 ` Will Deacon
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