From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5B51EC433E9 for ; Thu, 4 Mar 2021 00:03:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 33DC764FA0 for ; Thu, 4 Mar 2021 00:03:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236603AbhCDADI (ORCPT ); Wed, 3 Mar 2021 19:03:08 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54178 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1388006AbhCCUXR (ORCPT ); Wed, 3 Mar 2021 15:23:17 -0500 X-Greylist: delayed 4964 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Wed, 03 Mar 2021 12:22:37 PST Received: from desiato.infradead.org (desiato.infradead.org [IPv6:2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A8EFDC061756; Wed, 3 Mar 2021 12:22:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=NJRVHOfY/wAjmUPZBNz4qgJex3zmcTXiYgWDUNlTG8o=; b=eqA9t6kzaBOgSsX6JWQ6bNyGRh UgYeALN9opyR6KuSqGmP4uzPf+k1oBK6TCyU6a/1fX501vYjGmCpXFSWywGvkaonbPZhEayT++4iZ oODGrrJEmiuUlswEbZ3fyg6gI9kYBFgn9UR+KDU3zx1LGek7KNREdgasXMr6iw6BLvLokSybzj3o0 FNG0+dPAVRHOOozCESR//7yz71L+9+0rl3yqiyPbu8P6DvpStpnaONCATRQi3TmBKlvyzIITN694t lEto28QgNJ950rVl1iEY2vdIbNKBUcYGt3oxMUUHAEyvaVM0uFuclcgYh+03KSaFH8kTFiBm0BULu IrCyN89A==; Received: from j217100.upc-j.chello.nl ([24.132.217.100] helo=noisy.programming.kicks-ass.net) by desiato.infradead.org with esmtpsa (Exim 4.94 #2 (Red Hat Linux)) id 1lHXzy-006Opo-Az; Wed, 03 Mar 2021 20:21:53 +0000 Received: from hirez.programming.kicks-ass.net (hirez.programming.kicks-ass.net [192.168.1.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by noisy.programming.kicks-ass.net (Postfix) with ESMTPS id 795C73017B7; Wed, 3 Mar 2021 21:21:31 +0100 (CET) Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id 3FB8320B10DC6; Wed, 3 Mar 2021 21:21:31 +0100 (CET) Date: Wed, 3 Mar 2021 21:21:31 +0100 From: Peter Zijlstra To: "Liang, Kan" Cc: Vince Weaver , mingo@redhat.com, linux-kernel@vger.kernel.org, acme@kernel.org, mark.rutland@arm.com, alexander.shishkin@linux.intel.com, jolsa@redhat.com, namhyung@kernel.org, eranian@google.com, ak@linux.intel.com, stable@vger.kernel.org Subject: Re: [PATCH] Revert "perf/x86: Allow zero PEBS status with only single active event" Message-ID: References: <1614778938-93092-1-git-send-email-kan.liang@linux.intel.com> <9484ab6e-a6e5-bb72-106f-ed904e50fc0c@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <9484ab6e-a6e5-bb72-106f-ed904e50fc0c@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Mar 03, 2021 at 02:53:00PM -0500, Liang, Kan wrote: > On 3/3/2021 1:59 PM, Peter Zijlstra wrote: > > On Wed, Mar 03, 2021 at 05:42:18AM -0800, kan.liang@linux.intel.com wrote: > > > +++ b/arch/x86/events/intel/ds.c > > > @@ -2000,18 +2000,6 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs, struct perf_sample_d > > > continue; > > > } > > > - /* > > > - * On some CPUs the PEBS status can be zero when PEBS is > > > - * racing with clearing of GLOBAL_STATUS. > > > - * > > > - * Normally we would drop that record, but in the > > > - * case when there is only a single active PEBS event > > > - * we can assume it's for that event. > > > - */ > > > - if (!pebs_status && cpuc->pebs_enabled && > > > - !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1))) > > > - pebs_status = cpuc->pebs_enabled; > > > > Wouldn't something like: > > > > pebs_status = p->status = cpus->pebs_enabled; > > > > I didn't consider it as a potential solution in this patch because I don't > think it's a proper way that SW modifies the buffer, which is supposed to be > manipulated by the HW. Right, but then HW was supposed to write sane values and it doesn't do that either ;-) > It's just a personal preference. I don't see any issue here. We may try it. So I mostly agree with you, but I think it's a shame to unsupport such chips, HSW is still a plenty useable chip today.