From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65855C433E9 for ; Thu, 11 Mar 2021 17:45:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1A30564FEC for ; Thu, 11 Mar 2021 17:45:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230124AbhCKRoh (ORCPT ); Thu, 11 Mar 2021 12:44:37 -0500 Received: from vps0.lunn.ch ([185.16.172.187]:52400 "EHLO vps0.lunn.ch" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229871AbhCKRoH (ORCPT ); Thu, 11 Mar 2021 12:44:07 -0500 Received: from andrew by vps0.lunn.ch with local (Exim 4.94) (envelope-from ) id 1lKPLr-00AOQx-MT; Thu, 11 Mar 2021 18:43:59 +0100 Date: Thu, 11 Mar 2021 18:43:59 +0100 From: Andrew Lunn To: Ilya Lipnitskiy Cc: Sean Wang , Landen Chao , Vivien Didelot , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Jakub Kicinski , Matthias Brugger , Philipp Zabel , Russell King , netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH net-next,v2 1/3] net: dsa: mt7530: setup core clock even in TRGMII mode Message-ID: References: <20210311020954.842341-1-ilya.lipnitskiy@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20210311020954.842341-1-ilya.lipnitskiy@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Mar 10, 2021 at 06:09:52PM -0800, Ilya Lipnitskiy wrote: > A recent change to MIPS ralink reset logic made it so mt7530 actually > resets the switch on platforms such as mt7621 (where bit 2 is the reset > line for the switch). That exposed an issue where the switch would not > function properly in TRGMII mode after a reset. > > Reconfigure core clock in TRGMII mode to fix the issue. Hi Ilya For a patch series, netdev expects there to be a patch 0/X which explains the big picture. What do these patches as a whole do. This then gets used in the merge commit message. Andrew